Inventor

GONG ZHIWEI

US59 patents

⚠️ This page may combine multiple inventors who share the name “GONG ZHIWEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GONG ZHIWEI

NXP USA INC

EMI/RFI shielding for semiconductor device packages

Semiconductor device packaging warpage control

Semiconductor device packaging warpage control

Package integrated waveguide

Semiconductor package thermal spreader having integrated RF/EMI shielding and antenna elements

Plated opening with vent path

Radio frequency packages containing multilevel power substrates and associated fabrication methods

Semiconductor device packaging warpage control

Method, system, and apparatus for forming three-dimensional semiconductor device package with waveguide

Surface-mount amplifier devices

Semiconductor package thermal spreader having integrated EF/EMI shielding and antenna elements

Semiconductor device package having thermal dissipation feature and method therefor

Tie bar removal for semiconductor device packaging

Tie bar removal for semiconductor device packaging

Multichip packages with 3D integration

Molded packages with through-mold interconnects

Double-sided multichip packages

Semiconductor device packaging warpage control

Packaged devices with multiple planes of embedded electronic devices

Plated opening with vent path

Apparatus and methods for multi-die packaging

GONG ZHIWEI

Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits

EMI/RFI shielding for semiconductor device packages

Fan-out wafer level packages containing embedded ground plane interconnect structures and methods for the fabrication thereof

Method of forming a packaged semiconductor device

Packaging process to create wettable lead flank during board assembly

Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof

Semiconductor device packaging having substrate with pre-encapsulation through via formation

Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits

Apparatus and methods for quad flat no lead packaging

FREESCALE SEMICONDUCTOR INC

Apparatus and methods for multi-die packaging

Fan-out wafer level packages containing embedded ground plane interconnect structures and methods for the fabrication thereof

Exposed pad integrated circuit package with mold lock

Method of packaging integrated circuit die and device

Packaged devices with multiple planes of embedded electronic devices

Solder pad for semiconductor device package

Microelectronic packages having mold-embedded traces and methods for the production thereof

Three-dimensional integrated circuit systems in a package and methods therefor

VINCENT MICHAEL B

Microelectronic packages having mold-embedded traces and methods for the production thereof

Devices and stacked microelectronic packages with parallel conductors and intra-conductor isolator structures and methods of their fabrication

Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers

Microelectronic packages having trench vias and methods for the manufacture thereof

Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof

GAO WEI

Method for singulating electronic components from a substrate

Semiconductor devices and methods of assembling same

NXP BV

Low stress pad structure for packaged devices

Semiconductor device with cavity carrier and method therefor

YAP WENG F

System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof

XU JIANWEN

Back side alignment structure and manufacturing method for three-dimensional semiconductor device packages

MENG DOMINIC KOEY POH

Method of packaging semiconductor die