Inventor
LEAL GEORGE R
US23 patents
⚠️ This page may combine multiple inventors who share the name “LEAL GEORGE R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FREESCALE SEMICONDUCTOR INC
15 patentsUS6921975B2Jul 26, 2005
Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
FREESCALE SEMICONDUCTOR INC233 citations98
US6838776B2Jan 4, 2005
Circuit device with at least partial packaging and method for forming
FREESCALE SEMICONDUCTOR INC314 citations98
US7405102B2Jul 29, 2008
Methods and apparatus for thermal management in a multi-layer embedded chip structure
FREESCALE SEMICONDUCTOR INC69 citations97
US7361987B2Apr 22, 2008
Circuit device with at least partial packaging and method for forming
FREESCALE SEMICONDUCTOR INC75 citations97
US6844631B2Jan 18, 2005
Semiconductor device having a bond pad and method therefor
FREESCALE SEMICONDUCTOR INC161 citations95
US7892882B2Feb 22, 2011
Methods and apparatus for a semiconductor device package with improved thermal performance
FREESCALE SEMICONDUCTOR INC26 citations92
US7271013B2Sep 18, 2007
Semiconductor device having a bond pad and method therefor
FREESCALE SEMICONDUCTOR INC17 citations88
US8349666B1Jan 8, 2013
Fused buss for plating features on a semiconductor die
FREESCALE SEMICONDUCTOR INC15 citations84
US7950144B2May 31, 2011
Method for controlling warpage in redistributed chip packaging panels
FREESCALE SEMICONDUCTOR INC7 citations81
US7528069B2May 5, 2009
Fine pitch interconnect and method of making
FREESCALE SEMICONDUCTOR INC7 citations74
US10424521B2Sep 24, 2019
Programmable stitch chaining of die-level interconnects for reliability testing
FREESCALE SEMICONDUCTOR INC2 citations73
US9107303B2Aug 11, 2015
Warp compensated electronic assemblies
FREESCALE SEMICONDUCTOR INC5 citations73
US8368172B1Feb 5, 2013
Fused buss for plating features on a semiconductor die
FREESCALE SEMICONDUCTOR INC2 citations62
US7579219B2Aug 25, 2009
Semiconductor device with a protected active die region and method therefor
FREESCALE SEMICONDUCTOR INC0 citations42
US7553753B2Jun 30, 2009
Method of forming crack arrest features in embedded device build-up package and package thereof
FREESCALE SEMICONDUCTOR INC0 citations41
LEAL GEORGE R
5 patentsUS8877523B2Nov 4, 2014
Recovery method for poor yield at integrated circuit die panelization
LEAL GEORGE R3 citations61
US8072062B2Dec 6, 2011
Circuit device with at least partial packaging and method for forming
LEAL GEORGE R3 citations61
US9640469B2May 2, 2017
Matrix lid heatspreader for flip chip package
LEAL GEORGE R0 citations50
US9159643B2Oct 13, 2015
Matrix lid heatspreader for flip chip package
LEAL GEORGE R0 citations50
US8970026B2Mar 3, 2015
Methods and structures for reducing stress on die assembly
LEAL GEORGE R1 citations50