Inventor

GOWER KEVIN C

US126 patents

⚠️ This page may combine multiple inventors who share the name “GOWER KEVIN C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOWER KEVIN C

IBM

Heterogeneous recovery in a redundant memory system

System, method and storage medium for providing segment level sparing

High reliability memory module with a fault tolerant address and command bus

276-Pin buffered memory module with enhanced fault tolerance

High reliability memory module with a fault tolerant address and command bus

System, method and storage medium for providing a serialized memory interface with a bus repeater

Circuit and method for reading data transfers that are sent with a source synchronous clock signal

Digital temperature sensor (DTS) system to monitor temperature in a memory subsystem

Advanced memory device having reduced power and improved performance

System and method for error correction and detection in a memory system

System for enhancing the memory bandwidth available through a memory module

Buffered memory module with multiple memory device data interface ports supporting double the memory capacity

Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem

Systems and methods for providing distributed technology independent memory controllers

System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel

Method for supporting partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel

System, method and storage medium for providing fault detection and correction in a memory subsystem

System, method and storage medium for a multi-mode memory buffer device

System, method and storage medium for providing fault detection and correction in a memory subsystem

System, method and storage medium for bus calibration in a memory subsystem

System, method and storage medium for a memory subsystem command interface

System and method for providing a high fault tolerant memory system

Systems and methods for providing collision detection in a memory system

276-pin buffered memory module with enhanced fault tolerance

276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment

Systems and methods for providing performance monitoring in a memory system

High reliability memory module with a fault tolerant address and command bus

System, method and storage medium for providing data caching and data compression in a memory subsystem

Alternating current built in self test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test

Digital-to-analog converter (dac) for dynamic adjustment of off-chip driver pull-up and pull down impedance by providing a variable reference voltage to high frequency receiver and driver circuits for commercial memory

Test and bring-up of an enhanced cascade interconnect memory system

System, method and storage medium for providing a high speed test interface to a memory subsystem

System, method and storage medium for providing a high speed test interface to a memory subsystem

Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability

Memory testing system with algorithmic test data generation

High reliability memory module with a fault tolerant address and command bus

KIM KYU-HYOUN

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

GOWER KEVIN C

Performing error correction at a memory device level that is transparent to a memory channel

System for performing error correction operations in a memory hub device of a memory module

System for a combined error correction code and cyclic redundancy check code for a memory channel

DELL TIMOTHY J

Cascade interconnect memory system with enhanced reliability

System, method and storage medium for providing fault detection and correction in a memory subsystem

BUCHMANN PETER L

Power-on initialization and test for a cascade interconnect memory system

O'CONNOR JAMES A

High availability memory system

ALVES LUIZ C

Error correction and detection in a redundant memory system

MAULE WARREN EDWARD

Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device

LASTRAS-MONTANO LUIS A

Failing bus lane detection using syndrome analysis

COTEUS PAUL W

Voltage regulator bypass in memory device