Inventor

MAULE WARREN E

US147 patents

⚠️ This page may combine multiple inventors who share the name “MAULE WARREN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAULE WARREN E

IBM

Systems and methods for memory module power management

System, method and storage medium for providing segment level sparing

Efficient calibration of a data eye for memory devices

System, method and storage medium for providing a serialized memory interface with a bus repeater

Selective memory error reporting

System for enhancing the memory bandwidth available through a memory module

Buffered memory module with multiple memory device data interface ports supporting double the memory capacity

Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem

Systems and methods for providing distributed technology independent memory controllers

System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel

Method for supporting partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel

System, method and storage medium for providing fault detection and correction in a memory subsystem

System, method and storage medium for providing fault detection and correction in a memory subsystem

System, method and storage medium for a memory subsystem command interface

System and method for memory self-timed refresh for reduced power consumption

Efficient calibration of memory devices

System and method for providing DRAM device-level repair via address remappings external to the device

System, method and storage medium for providing data caching and data compression in a memory subsystem

System for reducing storage access latency with accessing main storage and data bus simultaneously

Fault isolation feature for an I/O or system bus

Memory and system configuration for programming a redundancy address in an electric system

Autonomous dram scrub and error counting

Error correction potency improvement via added burst beats in a dram access cycle

Error monitoring of a memory device containing embedded error correction

Error monitoring of a memory device containing embedded error correction

Efficient calibration of a data eye for memory devices

Detecting defective connections in stacked memory devices

Memory system connector

Detecting defective connections in stacked memory devices

Implementing decoupling devices inside a TSV DRAM stack

Partial cache line accesses based on memory access patterns

System and method for providing a non-power-of-two burst length in a memory system

Dynamic selection of a memory access size

System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller

System to provide memory system power reduction without reducing overall memory system performance

System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency

System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel

KIM KYU-HYOUN

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

GOWER KEVIN C

Performing error correction at a memory device level that is transparent to a memory channel

System for performing error correction operations in a memory hub device of a memory module

System for a combined error correction code and cyclic redundancy check code for a memory channel

DELL TIMOTHY J

Cascade interconnect memory system with enhanced reliability

System, method and storage medium for providing fault detection and correction in a memory subsystem

(unassigned)

Combination child&#39;s seat and armrest for a vehicle

O'CONNOR JAMES A

High availability memory system

HENDERSON JOAB D

Implementing decoupling devices inside a TSV DRAM stack

MAULE WARREN E

Display stand

ARIMILLI LAKSHMINARAYANA B

Cache management for partial cache line operations

Combination child's seat and armrest for a vehicle