Inventor
AVANCHA SASIKANTH
IN12 patents
⚠️ This page may combine multiple inventors who share the name “AVANCHA SASIKANTH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
10 patentsUS11977885B2May 7, 2024
Utilizing structured sparsity in systolic arrays
INTEL CORP2 citations72
US11681529B2Jun 20, 2023
Apparatuses, methods, and systems for access synchronization in a shared memory
INTEL CORP2 citations70
US11106464B2Aug 31, 2021
Apparatuses, methods, and systems for access synchronization in a shared memory
INTEL CORP2 citations70
US11275998B2Mar 15, 2022
Circuitry for low-precision deep learning
INTEL CORP2 citations69
US12405787B2Sep 2, 2025
Utilizing structured sparsity in systolic arrays
INTEL CORP0 citations61
US12039000B2Jul 16, 2024
Matrix operation optimization mechanism
INTEL CORP0 citations61
US11669329B2Jun 6, 2023
Instructions and logic for vector multiply add with zero skipping
INTEL CORP0 citations61
US11593454B2Feb 28, 2023
Matrix operation optimization mechanism
INTEL CORP0 citations61
US11314515B2Apr 26, 2022
Instructions and logic for vector multiply add with zero skipping
INTEL CORP0 citations61
US12399685B2Aug 26, 2025
Systolic array having support for output sparsity
INTEL CORP0 citations50