Inventor

DREPS DANIEL M

US117 patents

⚠️ This page may combine multiple inventors who share the name “DREPS DANIEL M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DREPS DANIEL M

IBM

276-Pin buffered memory module with enhanced fault tolerance

On-chip voltage controlled oscillator

Advanced memory device having reduced power and improved performance

System for providing open-loop quadrature clock generation

Power reduction in a parallel data communications interface using clock resynchronization

Controlling for variable impedance and voltage in a memory system

276-pin buffered memory module with enhanced fault tolerance

276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment

Data receiver with a programmable reference voltage to optimize timing jitter

Thevenins receiver

Interface having serializer including oscillator operating at first frequency and deserializer including oscillator operating at second frequency equals half first frequency for minimizing frequency interference

Simultaneous bi-directional I/O system

Phased locked loop with multiple voltage controlled oscillators

Overvoltage protection circuit

Systems and methods for signal detection

Self-healing chip-to-chip interface

Physical interface macros (PHYS) supporting heterogeneous electrical properties

Phase interpolator system and associated methods

Dynamic segment sparing and repair in a memory system

Signal history controlled slew-rate transmission method and bus interface transmitter

Dynamic recalibration mechanism for elastic interface

On-chip high frequency power supply noise sensor

Circuit for generating a tracking reference voltage

Signal transmission system with programmable voltage reference

Overvoltage protection circuit

276-pin buffered memory module with enhanced fault tolerance

276-pin buffered memory module with enhanced fault tolerance

Signal history controlled slew-rate transmission method and bus interface transmitter

Isolated semiconductor macro circuit

Multilayer ceramic electronic package with modulated mesh topology and alternating rods

Pre-transmission data reordering for a serial interface

Overvoltage protection circuit

Distributed serialized data buffer and a memory module for a cascadable and extended memory subsystem

Open-loop quadrature clock corrector and generator

Interface clock frequency switching using a computed insertion delay

Systems for signal detection

Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry

Fiber optic amplifier with active elements feedback circuit

Electronic gain cell

Vertically transitioning between substrate integrated waveguides (SIWs) within a multilayered printed circuit board (PCB)

Level shifting between interconnected chips having different voltage potentials

Oscillator failure detection circuit

Logic line driver system for providing an optimal driver characteristic

Jitter attenuation buffer structure

KIM KYU-HYOUN

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

Advanced memory device having improved performance, reduced power and increased reliability

DREPS DANIEL M

Controllable voltage reference driver for a memory system

Digital phase detector with zero phase offset

ARIMILLI RAVI K

Supporting multiple high bandwidth I/O controllers on a single chip