Inventor

SORNA MICHAEL A

US53 patents

⚠️ This page may combine multiple inventors who share the name “SORNA MICHAEL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SORNA MICHAEL A

IBM

On-chip system and method for measuring jitter tolerance of a clock and data recovery circuit

Method and apparatus for controlling common-mode output voltage in fully differential amplifiers

Probe interface assembly

On-chip electromigration monitoring system

Automatic adaptive equalization method and system for high-speed serial transmission link

Reference current generation system

Signal detector for high-speed serdes

Method and system for optimizing transmission and reception power levels in a communication system

High speed FIR transmitter

Low inductance side mount decoupling test structure

Linear voltage controlled oscillator transconductor with gain compensation

Front end interface for data receiver

Programmable peaking receiver and method

Coarse calibration circuit using variable step sizes to reduce jitter and a dynamic course calibration (DCC) circuit for a 2 GHz VCO

Optical power meter derived from common-mode voltage of optical transimpedance amplifier

System for measuring an eyewidth of a data signal in an asynchronous system

On-chip electromigration monitoring

Signal detector with calibration circuit arrangement

Dynamic threshold for VCO calibration

Multi-protocol driver slew rate calibration system for calibration slew rate control signal values

Out of band signaling enhancement for high speed serial driver

CML to CMOS signal converter

Data transceiver and method for equalizing the data eye of a differential input data signal

Reference current generation system and method

Structure for on-chip electromigration monitoring system

Automatic adaptive equalization method for high-speed serial transmission link

System and method for measuring a high speed signal

High speed serial data transmission encoder

Data communication system with self-test feature

Structure for apparatus for reduced loading of signal transmission elements

High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortion

Dynamically biased current gain voltage regulator with low quiescent power consumption

Damping of LC ringing in IC (integrated circuit) power distribution systems

Process independent source synchronous data capture apparatus and method

Regulated voltage boost charge pump for an integrated circuit device

Data communication system with self-test feature

Apparatus and method for reduced loading of signal transmission elements

Structure for robust cable connectivity test receiver for high-speed data receiver

Robust cable connectivity test receiver for high-speed data receiver

DREPS DANIEL M

Strobe offset in bidirectional memory strobe configurations

Strobe offset in bidirectional memory strobe configurations

Multi-use physical architecture

BULZACCHELLI JOHN FRANCIS

System and method for latency reduction in speculative decision feedback equalizers

XU HUIHAO

Structure for out of band signaling enhancement for high speed serial driver

BEUKEMA TROY J

Post-equalization amplitude latch-based channel characteristic measurement

GLOBALFOUNDRIES INC

Receiver deserializer latency trim

SORNA MICHAEL A

Leakage tolerant phase locked loop circuit device

KOSSEL MARCEL A

Clock feathered slew rate control system

MARVELL ASIA PTE LTD

Apparatus and related method to synchronize operation of serial repeater

GLOBALFOUNDRIES US 2 LLC

Transmitter serializer latency trim