Inventor

CHOU SHAO-YU

TW92 patents

⚠️ This page may combine multiple inventors who share the name “CHOU SHAO-YU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOU SHAO-YU

TAIWAN SEMICONDUCTOR MFG CO LTD

Multi-fuse memory cell circuit and method

Memory device with a fuse protection circuit

Memory device with a fuse protection circuit

ESD protection scheme using I/O pads

Memory with symmetric read current profile and read method thereof

Fuse structure

Reduced area efuse cell structure

Semiconductor device having fuse array and method of making the same

Memory circuit and method of operating same

Multi-fuse memory cell circuit and method

Single-gate-oxide power inverter and electrostatic discharge protection circuit

Memory circuit and method of operating same

Multi-fuse memory cell circuit and method

Single-gate-oxide power inverter and electrostatic discharge protection circuit

Integrated circuit layout, structure, system, and methods

Single-gate-oxide power inverter and electrostatic discharge protection circuit

Layout structure of memory array

Memory device with a fuse protection circuit

Memory device with a fuse protection circuit

Memory devices, semiconductor devices, and methods of operating a memory device

Memory with symmetric read current profile

Semiconductor device having fuse array and method of making the same

Memory with symmetric read current profile and read method thereof

Memory with symmetric read current profile and read method thereof

Semiconductor structures

Fusible structures and methods of manufacturing same

Reduced area eFuse cell structure

Voltage provision circuits with core transistors

Double metal layout for memory cells of a non-volatile memory

Electrical fuse bit cell and mask set

Memory device and operating method thereof

Multi-fuse memory cell circuit and method

Method and structure for reduce OTP cell area and leakage

Layout structures of memory array and related methods

System and method for reducing cell area and current leakage in anti-fuse cell array

TAIWAN SEMICONDUCTOR MFG

Output stage of a charge pump circuit providing relatively stable output voltage without voltage degradation

Low power charge pump regulating circuit

Products derived from embedded flash/EEPROM products

Circuit and method for VDD-tracking CVDD voltage supply

Robust 8T SRAM cell

Charge pump circuit reliability without degrading performance

Erase method of split gate flash memory reference cells

CHEN YEN-HUEI

Sense amplifier with low sensing margin and high device variation tolerance

Semiconductor structure with dummy polysilicon lines

WANG LI-WEN

High-speed SRAM

SRAM timing cell apparatus and methods

LEE CHENG HUNG

Low-leakage power supply architecture for an SRAM array

CHAN WEI MIN

Memory word-line driver having reduced power consumption

LIN TZU-KUEI

Memory device having a clock skew generator

CHOU SHAO-YU

Ultra-low voltage level shifting circuit