Inventor
SIMIONESCU HORIA
US20 patents
⚠️ This page may combine multiple inventors who share the name “SIMIONESCU HORIA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
AVAGO TECH INT SALES PTE LID
7 patentsUS10282301B2May 7, 2019
Method and system for hardware accelerated read-ahead caching
AVAGO TECH INT SALES PTE LID2 citations71
US10223009B2Mar 5, 2019
Method and system for efficient cache buffering supporting variable stripe sizes to enable hardware acceleration
AVAGO TECH INT SALES PTE LID1 citations71
US10423357B2Sep 24, 2019
Devices and methods for managing memory buffers
AVAGO TECH INT SALES PTE LID2 citations70
US10649906B2May 12, 2020
Method and system for hardware accelerated row lock for a write back volume
AVAGO TECH INT SALES PTE LID1 citations60
US10282116B2May 7, 2019
Method and system for hardware accelerated cache flush
AVAGO TECH INT SALES PTE LID0 citations50
US10528438B2Jan 7, 2020
Method and system for handling bad blocks in a hardware accelerated caching solution
AVAGO TECH INT SALES PTE LID0 citations39
US10394673B2Aug 27, 2019
Method and system for hardware accelerated copyback
AVAGO TECH INT SALES PTE LID0 citations39
LSI CORP
5 patentsUS9256384B2Feb 9, 2016
Method and system for reducing write latency in a data storage system by using a command-push model
LSI CORP10 citations84
US9542101B2Jan 10, 2017
System and methods for performing embedded full-stripe write operations to a data volume with data elements distributed across multiple modules
LSI CORP7 citations83
US9292228B2Mar 22, 2016
Selective raid protection for cache memory
LSI CORP3 citations72
US9244868B2Jan 26, 2016
Leased lock in active-active high availability DAS systems
LSI CORP2 citations61
US9274713B2Mar 1, 2016
Device driver, method and computer-readable medium for dynamically configuring a storage controller based on RAID type, data alignment with a characteristic of storage elements and queue depth in a cache
LSI CORP2 citations58
AVAGO TECHNOLOGIES GENERAL IP
4 patentsUS9734062B2Aug 15, 2017
System and methods for caching a small size I/O to improve caching device endurance
AVAGO TECHNOLOGIES GENERAL IP1 citations51
US10108359B2Oct 23, 2018
Method and system for efficient cache buffering in a system having parity arms to enable hardware acceleration
AVAGO TECHNOLOGIES GENERAL IP0 citations50
US10078460B2Sep 18, 2018
Memory controller utilizing scatter gather list techniques
AVAGO TECHNOLOGIES GENERAL IP0 citations50
US9965397B2May 8, 2018
Fast read in write-back cached memory
AVAGO TECHNOLOGIES GENERAL IP1 citations40