Inventor
YEE ABRAHAM
US20 patents
⚠️ This page may combine multiple inventors who share the name “YEE ABRAHAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
16 patentsUS5723896AMar 3, 1998
Integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate
LSI LOGIC CORP72 citations96
US5721151AFeb 24, 1998
Method of fabricating a gate array integrated circuit including interconnectable macro-arrays
LSI LOGIC CORP86 citations95
US5622882AApr 22, 1997
Method of making a CMOS dynamic random-access memory (DRAM)
LSI LOGIC CORP25 citations92
US5593918AJan 14, 1997
Techniques for forming superconductive lines
LSI LOGIC CORP20 citations92
US5508211AApr 16, 1996
Method of making integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate
LSI LOGIC CORP19 citations92
US5516731AMay 14, 1996
High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance
LSI LOGIC CORP21 citations90
US5358886AOct 25, 1994
Method of making integrated circuit structure with programmable conductive electrode/interconnect material
LSI LOGIC CORP24 citations90
US5644143AJul 1, 1997
Method for protecting a semiconductor device with a superconductive line
LSI LOGIC CORP6 citations74
US5679598AOct 21, 1997
Method of making a CMOS dynamic random-access memory (DRAM)
LSI LOGIC CORP14 citations73
US5538907AJul 23, 1996
Method for forming a CMOS integrated circuit with electrostatic discharge protection
LSI LOGIC CORP11 citations73
US6093936AJul 25, 2000
Integrated circuit with isolation of field oxidation by noble gas implantation
LSI LOGIC CORP9 citations72
US5874754AFeb 23, 1999
Microelectronic cells with bent gates and compressed minimum spacings, and method of patterning interconnections for the gates
LSI LOGIC CORP11 citations71
US5561319AOct 1, 1996
Integrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereof
LSI LOGIC CORP12 citations71
US5440154AAug 8, 1995
Non-rectangular MOS device configurations for gate array type integrated circuits
LSI LOGIC CORP6 citations71
US5648290AJul 15, 1997
Method of making a CMOS dynamic random-access memory (DRAM)
LSI LOGIC CORP4 citations62
US5796130AAug 18, 1998
Non-rectangular MOS device configurations for gate array type integrated circuits
LSI LOGIC CORP4 citations60
NVIDIA CORP
3 patentsUS9716051B2Jul 25, 2017
Open solder mask and or dielectric to increase lid or ring thickness and contact area to improve package coplanarity
NVIDIA CORP2 citations70
US10032692B2Jul 24, 2018
Semiconductor package structure
NVIDIA CORP3 citations68
US9760132B2Sep 12, 2017
Stiffening electronic packages by disposing a stiffener ring between substrate center area and conductive pad
NVIDIA CORP0 citations49