Inventor
PAVESI MARCO
IT6 patents
Patents
6 patentsUS6970966B2Nov 29, 2005
System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol
ITALTEL SPA65 citations94
US7130942B2Oct 31, 2006
Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding
ITALTEL SPA36 citations90
US7289502B1Oct 30, 2007
Method and device for routing or compressing packets destination address containing classless address
ITALTEL SPA17 citations80
US6549536B1Apr 15, 2003
Method of address compression for cell-based and packet-based protocols and hardware implementations thereof
ITALTEL SPA8 citations72
US6964574B2Nov 15, 2005
Daughter board for a prototyping system
ITALTEL SPA8 citations66
US7036095B2Apr 25, 2006
Clock generation system for a prototyping apparatus
ITALTEL SPA5 citations57