Inventor

DALY DAVID M

US34 patents

⚠️ This page may combine multiple inventors who share the name “DALY DAVID M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DALY DAVID M

IBM

Private memory table for reduced memory coherence traffic

Using spare capacity in solid state drives

Private memory table for reduced memory coherence traffic

Redundant transactions for detection of timing sensitive errors

Actively controlled performance clothing

Using spare capacity in solid state drives

Thread-based cache content saving for task switching

Thread-based cache content saving for task switching

Transactions for checkpointing and reverse execution

Add-on memory coherence directory

Add-on memory coherence directory

Method and apparatus for cache memory data processing

Thread-based cache content saving for task switching

Private memory table for reduced memory coherence traffic

Method and apparatus for cache memory data processing

Prefetch threshold for cache restoration

Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor

Using spare capacity in solid state drives

Detection of hardware errors using redundant transactions for system test

Private memory table for reduced memory coherence traffic

Redundant transactions for detection of timing sensitive errors

Locking power supplies

DALY DAVID M

Prediction based priority scheduling

Weighted history allocation predictor algorithm in a hybrid cache

Weighted history allocation predictor algorithm in a hybrid cache

Dynamic inclusive policy in a hybrid cache hierarchy using hit rate

Memory bus write prioritization

Prediction based priority scheduling

Power reduction in server memory system

Cradle for controlling abnormal sitting postures

Coordinated writeback of dirty cachelines

Dynamic inclusive policy in a hybrid cache hierarchy using bandwidth

Coordinated writeback of dirty cachelines

Memory bus write prioritization