Inventor

KHELLAH MUHAMMAD

US30 patents

⚠️ This page may combine multiple inventors who share the name “KHELLAH MUHAMMAD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KHELLAH MUHAMMAD

INTEL CORP

Floating-body DRAM using write word line for increased retention time

SRAM array with dynamic voltage for reducing active leakage power

All-digital voltage monitor (ADVM) with single-cycle latency

Floating-body DRAM using write word line for increased retention time

Method and system of temporal-domain feature extraction for automatic speech recognition

All-digital voltage monitor (ADVM) with single-cycle latency

Assist circuit for memory

Adaptive voltage system for aging guard-band reduction

Charge injector with integrated level shifter for localized mitigation of supply voltage droop

Detecting keywords in audio using a spiking neural network

All-digital closed loop voltage generator

Current steering level-shifter

Circuits and methods for supply voltage detection and timing monitoring

Distributed and scalable all-digital low dropout integrated voltage regulator

Calibrated biasing of sleep transistor in integrated circuits

Unified retention and wake-up clamp apparatus and method

Current steering level-shifter

Reliable digital low dropout voltage regulator

Energy efficient memory array with optimized burst read and write data access

Minimum delay error detection and correction for pulsed latches

Retention minimum voltage determination techniques

Memory cell with retention using resistive memory

Assist circuit for memory

Low power retention flip-flop with level-sensitive scan circuitry

KHELLAH MUHAMMAD

Memory cell supply voltage control based on error detection

Memory cell supply voltage control based on error detection

DE VIVEK

Circuits and methods for reducing minimum supply for register file cells

Circuits and methods for reducing minimum supply for register file cells

CHISHTI ZESHAN A

Performing multi-bit error correction on a cache line

GEUSKENS BIBICHE

Register file circuits with P-type evaluation