Inventor
HELLER JR THOMAS J
US34 patents
⚠️ This page may combine multiple inventors who share the name “HELLER JR THOMAS J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
17 patentsUS8028290B2Sep 27, 2011
Multiple-core processor supporting multiple instruction set architectures
IBM54 citations96
US7401240B2Jul 15, 2008
Method for dynamically managing power in microprocessor chips according to present processing demands
IBM52 citations95
US7469321B2Dec 23, 2008
Software process migration between coherency regions without cache purges
IBM24 citations92
US6052771AApr 18, 2000
Microprocessor with pipeline synchronization
IBM39 citations92
US6047367AApr 4, 2000
Microprocessor with improved out of order support
IBM23 citations92
US9430153B2Aug 30, 2016
Garbage collection and other management of memory heaps
IBM6 citations84
US9104427B2Aug 11, 2015
Computing system with transactional memory using millicode assists
IBM6 citations84
US7484043B2Jan 27, 2009
Multiprocessor system with dynamic cache coherency regions
IBM13 citations83
US8032736B2Oct 4, 2011
Methods, apparatus and articles of manufacture for regaining memory consistency after a trap via transactional memory
IBM12 citations81
US8738862B2May 27, 2014
Transactional memory system with efficient cache support
IBM2 citations63
US8667231B2Mar 4, 2014
Transactional memory system with efficient cache support
IBM2 citations63
US7647519B2Jan 12, 2010
System and computer program product for dynamically managing power in microprocessor chips according to present processing demands
IBM3 citations62
US10146685B2Dec 4, 2018
Garbage collection and other management of memory heaps
IBM0 citations52
US9772941B2Sep 26, 2017
Garbage collection and other management of memory heaps
IBM0 citations52
US9740608B2Aug 22, 2017
Garbage collection and other management of memory heaps
IBM0 citations52
US8819352B2Aug 26, 2014
Hybrid Transactional Memory (HybridTM)
IBM0 citations52
US9146678B2Sep 29, 2015
High throughput hardware acceleration using pre-staging buffers
IBM0 citations42
HELLER JR THOMAS J
11 patentsUS8117403B2Feb 14, 2012
Transactional memory system which employs thread assists using address history tables
HELLER JR THOMAS J49 citations94
US8095750B2Jan 10, 2012
Transactional memory system with fast processing of common conflicts
HELLER JR THOMAS J32 citations92
US8095741B2Jan 10, 2012
Transactional memory computing system with support for chained transactions
HELLER JR THOMAS J32 citations86
US8788672B2Jul 22, 2014
Microprocessor with software control over allocation of shared resources among multiple virtual servers
HELLER JR THOMAS J15 citations84
US8676976B2Mar 18, 2014
Microprocessor with software control over allocation of shared resources among multiple virtual servers
HELLER JR THOMAS J8 citations84
US8516202B2Aug 20, 2013
Hybrid transactional memory system (HybridTM) and method
HELLER JR THOMAS J7 citations84
US8688920B2Apr 1, 2014
Computing system with guest code support of transactional memory
HELLER JR THOMAS J6 citations73
US8417974B2Apr 9, 2013
Power efficient stack of multicore microprocessors
HELLER JR THOMAS J6 citations73
US9009452B2Apr 14, 2015
Computing system with transactional memory using millicode assists
HELLER JR THOMAS J2 citations63
US8566524B2Oct 22, 2013
Transactional memory system with efficient cache support
HELLER JR THOMAS J4 citations63
US8862786B2Oct 14, 2014
Program execution with improved power efficiency
HELLER JR THOMAS J0 citations42