Inventor

PAPAGEORGIOU VASSILIOS

US24 patents

⚠️ This page may combine multiple inventors who share the name “PAPAGEORGIOU VASSILIOS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAPAGEORGIOU VASSILIOS

KRONHOLZ STEPHAN

Reducing silicide resistance in silicon/germanium-containing drain/source regions of transistors

Semiconductor element formed in a crystalline substrate material and comprising an embedded in situ doped semiconductor material

Transistor device comprising an embedded semiconductor alloy having an asymmetric configuration

Transistor with an embedded strain-inducing material having a gradually shaped configuration

Transistor with an embedded strain-inducing material having a gradually shaped configuration

Integration of semiconductor alloys in PMOS and NMOS transistors by using a common cavity etch process

Adjusting of a non-silicon fraction in a semiconductor alloy during transistor fabrication by an intermediate oxidation process

ADVANCED MICRO DEVICES INC

Drive current increase in transistors by asymmetric amorphization implantation

System and method for testing packaged devices using time domain reflectometry

Method and device for determining an operational lifetime of an integrated circuit device

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation

GLOBALFOUNDRIES INC

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

Adjusting configuration of a multiple gate transistor by controlling individual fins

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

HOENTSCHEL JAN

Adjusting configuration of a multiple gate transistor by controlling individual fins

Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material

In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profile

Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material

MOWRY ANTHONY

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

PAPAGEORGIOU VASSILIOS

Transistor device comprising an asymmetric embedded semiconductor alloy

MULFINGER G ROBERT

Graded well implantation for asymmetric transistors having reduced gate electrode pitches