Inventor
JAYACHANDRAN SOWMIYA
US11 patents
⚠️ This page may combine multiple inventors who share the name “JAYACHANDRAN SOWMIYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
7 patentsUS9202547B2Dec 1, 2015
Managing disturbance induced errors
INTEL CORP8 citations84
US9818458B1Nov 14, 2017
Techniques for entry to a lower power state for a memory device
INTEL CORP5 citations82
US9792963B2Oct 17, 2017
Managing disturbance induced errors
INTEL CORP2 citations73
US9916104B2Mar 13, 2018
Techniques for entry to a lower power state for a memory device
INTEL CORP4 citations71
US11036412B2Jun 15, 2021
Dynamically changing between latency-focused read operation and bandwidth-focused read operation
INTEL CORP3 citations70
US8001444B2Aug 16, 2011
ECC functional block placement in a multi-channel mass storage device
INTEL CORP3 citations61
US10153015B2Dec 11, 2018
Managing disturbance induced errors
INTEL CORP0 citations52
MICRON TECHNOLOGY INC
3 patentsUS10437307B2Oct 8, 2019
Apparatuses and methods for exiting low power states in memory devices
MICRON TECHNOLOGY INC1 citations71
US9778723B2Oct 3, 2017
Apparatuses and methods for exiting low power states in memory devices
MICRON TECHNOLOGY INC2 citations71
US11249531B2Feb 15, 2022
Apparatuses and methods for exiting low power states in memory devices
MICRON TECHNOLOGY INC0 citations61