Inventor
ADAMS CHAD A
US25 patents
⚠️ This page may combine multiple inventors who share the name “ADAMS CHAD A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
17 patentsUS7827018B2Nov 2, 2010
Method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects
IBM18 citations84
US9087607B2Jul 21, 2015
Implementing sense amplifier for sensing local write driver with bootstrap write assist for SRAM arrays
IBM15 citations82
US10381098B2Aug 13, 2019
Memory interface latch with integrated write-through and fence functions
IBM2 citations72
US10229748B1Mar 12, 2019
Memory interface latch with integrated write-through function
IBM4 citations72
US7760541B2Jul 20, 2010
Functional float mode screen to test for leakage defects on SRAM bitlines
IBM2 citations63
US7506282B2Mar 17, 2009
Apparatus and methods for predicting and/or calibrating memory yields
IBM4 citations62
US7239559B2Jul 3, 2007
Methods and apparatus for accessing memory
IBM4 citations62
US10916323B2Feb 9, 2021
Memory interface latch with integrated write-through and fence functions
IBM0 citations61
US9007857B2Apr 14, 2015
SRAM global precharge, discharge, and sense
IBM2 citations60
US7983080B2Jul 19, 2011
Non-body contacted sense amplifier with negligible history effect
IBM2 citations60
US7224594B2May 29, 2007
Glitch protect valid cell and method for maintaining a desired state value
IBM4 citations59
US9183896B1Nov 10, 2015
Deep sleep wakeup of multi-bank memory
IBM3 citations57
US9007858B2Apr 14, 2015
SRAM global precharge, discharge, and sense
IBM0 citations50
US9251869B2Feb 2, 2016
Deep sleep wakeup of multi-bank memory
IBM0 citations46
US9183906B2Nov 10, 2015
Fine granularity power gating
IBM0 citations42
US8754691B2Jun 17, 2014
Memory array pulse width control
IBM0 citations41
US7388773B2Jun 17, 2008
Random access memory with a plurality of symmetrical memory cells
IBM0 citations34
ADAMS CHAD A
7 patentsUS8233342B2Jul 31, 2012
Apparatus and method for implementing write assist for static random access memory arrays
ADAMS CHAD A43 citations93
US8279687B2Oct 2, 2012
Single supply sub VDD bit-line precharge SRAM and method for level shifting
ADAMS CHAD A31 citations92
US8593890B2Nov 26, 2013
Implementing supply and source write assist for SRAM arrays
ADAMS CHAD A31 citations89
US8274848B2Sep 25, 2012
Level shifter for use with memory arrays
ADAMS CHAD A2 citations60
US8451668B1May 28, 2013
Implementing column redundancy steering for memories with wordline repowering
ADAMS CHAD A0 citations51
US8108739B2Jan 31, 2012
High-speed testing of integrated devices
ADAMS CHAD A1 citations51
US8659937B2Feb 25, 2014
Implementing low power write disabled local evaluation for SRAM
ADAMS CHAD A0 citations49