Inventor
FOUTZ BRIAN
US13 patents
⚠️ This page may combine multiple inventors who share the name “FOUTZ BRIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
8 patentsUS7926012B1Apr 12, 2011
Design-For-testability planner
CADENCE DESIGN SYSTEMS INC26 citations90
US8001433B1Aug 16, 2011
Scan testing architectures for power-shutoff aware systems
CADENCE DESIGN SYSTEMS INC15 citations84
US7979764B2Jul 12, 2011
Distributed test compression for integrated circuits
CADENCE DESIGN SYSTEMS INC16 citations82
US11947887B1Apr 2, 2024
Test-point flop sharing with improved testability in a circuit design
CADENCE DESIGN SYSTEMS INC1 citations59
US12007440B1Jun 11, 2024
Systems and methods for scan chain stitching
CADENCE DESIGN SYSTEMS INC1 citations58
US12412014B1Sep 9, 2025
IC chip with IC design modification detection
CADENCE DESIGN SYSTEMS INC0 citations49
US12511462B1Dec 30, 2025
Physical awareness of test-point sharing in a circuit design
CADENCE DESIGN SYSTEMS INC0 citations47
US12475288B1Nov 18, 2025
Clock-based test-point flop sharing in a circuit design
CADENCE DESIGN SYSTEMS INC0 citations47
HEWLETT PACKARD DEVELOPMENT CO
5 patentsUS6996515B1Feb 7, 2006
Enabling verification of a minimal level sensitive timing abstraction model
HEWLETT PACKARD DEVELOPMENT CO37 citations92
US6611948B1Aug 26, 2003
Modeling circuit environmental sensitivity of a minimal level sensitive timing abstraction model
HEWLETT PACKARD DEVELOPMENT CO32 citations92
US6609233B1Aug 19, 2003
Load sensitivity modeling in a minimal level sensitive timing abstraction model
HEWLETT PACKARD DEVELOPMENT CO23 citations92
US6604227B1Aug 5, 2003
Minimal level sensitive timing abstraction model capable of being used in general static timing analysis tools
HEWLETT PACKARD DEVELOPMENT CO37 citations92
US6581197B1Jun 17, 2003
Minimal level sensitive timing representative of a circuit path
HEWLETT PACKARD DEVELOPMENT CO25 citations92