Inventor

LEE DANA

US133 patents

⚠️ This page may combine multiple inventors who share the name “LEE DANA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE DANA

SANDISK TECHNOLOGIES INC

Word line dependent programming in a memory device

Recovery of partially programmed block in non-volatile memory

On chip dynamic read level scan and error detection for nonvolatile storage

Systems and methods for lower page writes

Simultaneous sensing of multiple wordlines and detection of NAND failures

On chip dynamic read for non-volatile storage

Systems and methods for sampling data at a non-volatile memory system

Ramping pass voltage to enhance channel boost in memory device

On chip dynamic read level scan and error detection for nonvolatile storage

Partial block erase for open block reading in non-volatile memory

Non-volatile memory with prior state sensing

Storage module and method for using healing effects of a quarantine process

Systems and methods for lower page writes

Erase speed adjustment for endurance of non-volatile storage

Reducing the impact of interference during programming

Defect or program disturb detection with full data recovery capability

Erased state reading

SILICON STORAGE TECH INC

Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation

Self aligned method of forming a semiconductor memory array of floating gate memory cells and a memory array made thereby

Differential non-volatile content addressable memory cell and array using phase changing resistor storage elements

Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region, and a memory array made thereby

Non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation

Semiconductor memory array of floating gate memory cells with buried floating gate

Self aligned method of forming a semiconductor memory array of floating gate memory cells, and a memory array made thereby

Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing

Isolation-less, contact-less array of nonvolatile memory cells each having a floating gate for storage of charges, and methods of manufacturing, and operating therefor

SANDISK CORP

Reducing the impact of interference during programming

Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data

Programming algorithm to reduce disturb with minimal extra time penalty

Regulation of source potential to combat cell source IR drop

Systems for programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data

Systems for programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages

Programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages

Two pass erase for non-volatile storage

SANDISK TECHNOLOGIES LLC

Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same

Read scrub with adaptive counter management

Accelerated physical secure erase

Three-dimensional memory structure having a back gate electrode

Techniques for reducing read disturb in partially written blocks of non-volatile memory

WESTERN DIGITAL TECH INC

Temperature variation compensation

Temperature variation compensation

MICROSOFT CORP

Display screen with graphical user interface

SPROUSE STEVEN T

Flash memory with targeted read scrub algorithm

SHARON ERAN

Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures

IBM

Self-aligned non-volatile random access memory cell and process to make the same

LI YAN

Detection of word-line leakage in memory arrays

DUTTA DEEPANSHU

On chip dynamic read for non-volatile storage

D ABREU MANUEL ANTONIO

System and method responsive to a rate of change of a performance parameter of a memory

AVILA CHRIS

Scrub techniques for use with dynamic read

KHANDELWAL ANUBHAV

Reducing neighbor read disturb