Inventor

MAYILADUTHURAI RAMESH S

US2 patents

Patents

2 patents

US7251795B2Jul 31, 2007

Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design

CADENCE DESIGN SYSTEMS INC10 citations81

US7260792B2Aug 21, 2007

Modeling a mixed-language mixed-signal design

CADENCE DESIGN SYSTEMS INC9 citations70