Inventor

PELEG ALEXANDER D

IL48 patents

⚠️ This page may combine multiple inventors who share the name “PELEG ALEXANDER D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PELEG ALEXANDER D

INTEL CORP

Method for performing multiply-add operations on packed data

Method and apparatus for performing multiply-add operations on packed data

Method and apparatus for multiplying and accumulating data samples and complex coefficients

Method and apparatus for multiplying and accumulating complex numbers in a digital filter

Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations

Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner

Apparatus for performing multiply-add operations on packed data

Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file

Method and apparatus for performing multiply and accumulate operations on packed data

Apparatus for performing packed shift operations

Method and apparatus for multiplying and accumulating complex numbers in a digital filter

Apparatus for performing packed shift operations

Method for executing instructions that operate on different data types stored in the same single logical register file

Computer system for performing complex digital filters

System for signal processing using multiply-add operations

Emptying packed data state during execution of packed data instructions

Computer implemented method for transferring packed data between register files and memory

Method for transposing a two-dimensional array

Manipulating video and audio signals using a processor which supports SIMD instructions

Executing different instructions that cause different data type operations to be performed on single logical register file

Method and apparatus for multiplying and accumulating complex numbers in a digital filter

Computer system performing a two-dimensional rotation of packed data representing multimedia information

Method for performing complex fast fourier transforms (FFT&#39;s)

Method and apparatus for performing multiply-add operations on packed data

Processor with instructions that operate on different data types stored in the same single logical register file

Emptying packed data state during execution of packed data instructions

System for providing the absolute difference of unsigned values

Microarchitecture for implementing an instruction to clear the tags of a stack reference register file

Processor with instructions that operate on different data types stored in the same single logical register file

Method and an apparatus for providing the absolute difference of unsigned values

Method and apparatus for performing packed shift operations

Method and apparatus for performing multiply-add operations on packed data

Method and apparatus for providing packed shift operations in a processor

Method and apparatus for providing packed shift operations in a processor

Method and apparatus for providing packed shift operations in a processor

Methods and apparatuses to clear state for operation of a stack

Processor capable of executing packed shift operations

Orderly storing of corresponding packed bytes from first and second source registers in result register

Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements

Interleaving half of packed data elements of size specified in instruction and stored in two source registers

Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers

Packing in destination register half of each element with saturation from two source packed data registers

Packing odd bytes from two source registers of packed data

Emptying packed data state during execution of packed data instructions

Computer implemented method for providing a two dimensional rotation of packed data

Method and apparatus for executing packed shift operations

PELEG ALEXANDER D

Processor for performing multiply-add operations on packed data

Processor for performing multiply-add operations on packed data

Method for performing complex fast fourier transforms (FFT's)