Inventor

DEWEY III LEWIS WILLIAM

US6 patents

⚠️ This page may combine multiple inventors who share the name “DEWEY III LEWIS WILLIAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

3 patents

US7075532B2Jul 11, 2006

Robust tetrahedralization and triangulation method with applications in VLSI layout design and manufacturability

IBM13 citations82

US11176308B1Nov 16, 2021

Extracting parasitic capacitance from circuit designs

IBM3 citations68

US11314916B2Apr 26, 2022

Capacitance extraction

IBM1 citations57

DEWEY III LEWIS WILLIAM

2 patents

US8201122B2Jun 12, 2012

Computing resistance sensitivities with respect to geometric parameters of conductors with arbitrary shapes

DEWEY III LEWIS WILLIAM99 citations92

US8136069B2Mar 13, 2012

Accurate approximation of resistance in a wire with irregular biasing and determination of interconnect capacitances in VLSI layouts in the presence of Catastrophic Optical Proximity Correction

DEWEY III LEWIS WILLIAM0 citations38

ELFADEL IBRAHIM M

1 patent

US8239804B2Aug 7, 2012

Method for calculating capacitance gradients in VLSI layouts using a shape processing engine

ELFADEL IBRAHIM M4 citations60