Inventor

SREENIVASAN RAGHAVASIMHAN

US39 patents

⚠️ This page may combine multiple inventors who share the name “SREENIVASAN RAGHAVASIMHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SREENIVASAN RAGHAVASIMHAN

IBM

Borderless contacts for semiconductor transistors

Locally isolated protected bulk finfet semiconductor device

Method and structure for robust finFET replacement metal gate integration

Prevention of fin erosion for semiconductor devices

Embedded source/drains with epitaxial oxide underlayer

Prevention of fin erosion for semiconductor devices

Self-aligned biosensors with enhanced sensitivity

Modified fin cut after epitaxial growth

Self aligned contact with improved robustness

Semiconductor fabrication method using stop layer

Reduced external resistance finFET device

Self-aligned contacts for replacement metal gate transistors

Locally isolated protected bulk FinFET semiconductor device

FinFET spacer without substrate gouging or spacer foot

Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition

Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition

MIM capacitor with enhanced capacitance formed by selective epitaxy

Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition

Locally isolated protected bulk FinFET semiconductor device

FinFET with silicon germanium stressor and method of forming

FinFET semiconductor device having increased gate height control

Self-aligned biosensors with enhanced sensitivity

Self-aligned contacts for replacement metal gate transistors

Back-gated substrate and semiconductor device, and related method of fabrication

Replacement metal gate including dielectric gate material

Epitaxially grown quantum well finFETs for enhanced pFET performance

GLOBALFOUNDRIES INC

Method of fabricating a semiconductor device including embedded crystalline back-gate bias planes

FinFET semiconductor device having increased gate height control

FinFET with crystalline insulator

Dual epitaxy region integration

Semiconductor device including embedded crystalline back-gate bias planes, related design structure and method of fabrication

Electrically controlled optical fuse and method of fabrication

Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)

CHENG KANGGUO

Self aligned contact with improved robustness

Electrically controlled optical fuse and method of fabrication

HARTIG MICHAEL J

Semiconductor plural gate lengths

GLOBAL FOUNDRIES U S 2 LLC

Self-aligned gate contact structure

RENESAS ELECTRONICS CORP

Semiconductor device and method of manufacturing the semiconductor device

DORIS BRUCE B

Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)