Inventor

CHENG CHENG-WEI

US126 patents

⚠️ This page may combine multiple inventors who share the name “CHENG CHENG-WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHENG CHENG-WEI

IBM

Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts

III-V finFETs on silicon substrate

III-V lateral bipolar integration with silicon

Polarization free gallium nitride-based photonic devices on nanopatterned silicon

Enhanced defect reduction for heteroepitaxy by seed shape engineering

Selective epitaxy using epitaxy-prevention layers

Graded buffer epitaxy in aspect ratio trapping

Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts

Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth

Complementary metal-oxide-semiconductor structure with III-V and silicon germanium transistors on insulator

Selective gallium nitride regrowth on (100) silicon

Dual phase gallium nitride material formation on (100) silicon

Co-integration of elemental semiconductor devices and compound semiconductor devices

Co-integration of elemental semiconductor devices and compound semiconductor devices

Gate-all-around field effect transistor using template-assisted-slective-epitaxy

Multi-state transistor devices with multiple threshold voltage channels

III-V semiconductor devices with selective oxidation

Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films

III-V semiconductor devices with selective oxidation

Surface roughness of III-V fin formed on silicon sidewall by implementing sacrificial buffers

Enhanced defect reduction for heteroepitaxy by seed shape engineering

Selective epitaxy using epitaxy-prevention layers

Asymmetric III-V MOSFET on silicon substrate

III-V photonic integrated circuits on silicon substrate

Asymmetric III-V MOSFET on silicon substrate

Integration of III-V compound materials on silicon

Laser structure on silicon using aspect ratio trapping growth

Reduced current leakage semiconductor device

Overlapped III-V finFET with doped semiconductor extensions

T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator

PCM cell with resistance drift correction

PCM cell with resistance drift correction

III-V transistor device with self-aligned doped bottom barrier

Smoothing surface roughness of III-V semiconductor fins formed from silicon mandrels by regrowth

III-V MOSFET with self-aligned diffusion barrier

Reduced current leakage semiconductor device

Preparation of low defect density of III-V on Si for device fabrication

Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material

Crystalline thin film photovoltaic cell

Selective gallium nitride regrowth on (100) silicon

Overlapped III-V finfet with doped semiconductor extensions

Integration of Ge-containing fins and compound semiconductor fins

Crack control for substrate separation

High throughput epitaxial lift off for flexible electronics

Self-formation of high-density defect-free and aligned nanostructures

GLOBALFOUNDRIES INC

Multiple via structure and method

III-V lasers with integrated silicon photonic circuits

BEDELL STEPHEN W

Flexible III-V solar cell structure

CHENG CHENG-WEI

High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate

TAIWAN SEMICONDUCTOR MFG CO LTD

Active region design layout