Inventor

SHIU KUEN-TING

US105 patents

⚠️ This page may combine multiple inventors who share the name “SHIU KUEN-TING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHIU KUEN-TING

IBM

Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts

III-V finFETs on silicon substrate

Polarization free gallium nitride-based photonic devices on nanopatterned silicon

Enhanced defect reduction for heteroepitaxy by seed shape engineering

Graded buffer epitaxy in aspect ratio trapping

Nanowire field effect transistor (FET) and method for fabricating the same

Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts

Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth

Complementary metal-oxide-semiconductor structure with III-V and silicon germanium transistors on insulator

Selective gallium nitride regrowth on (100) silicon

Dual phase gallium nitride material formation on (100) silicon

Co-integration of elemental semiconductor devices and compound semiconductor devices

Co-integration of elemental semiconductor devices and compound semiconductor devices

Dielectric equivalent thickness and capacitance scaling for semiconductor devices

Enhanced defect reduction for heteroepitaxy by seed shape engineering

Nanowire field effect transistor (FET) and method for fabricating the same

III-V photonic integrated circuits on silicon substrate

Compound finFET device including oxidized III-V fin isolator

Integration of III-V compound materials on silicon

Laser structure on silicon using aspect ratio trapping growth

Overlapped III-V finFET with doped semiconductor extensions

T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator

Preparation of low defect density of III-V on Si for device fabrication

Techniques for fabricating reduced-line-edge-roughness trenches for aspect ratio trapping

Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material

Nanowires formed by employing solder nanodots

Crystalline thin film photovoltaic cell

III-V semiconductor device having self-aligned contacts

Selective gallium nitride regrowth on (100) silicon

Reduced S/D contact resistance of III-V mosfet using low temperature metal-induced crystallization of n+ Ge

Overlapped III-V finfet with doped semiconductor extensions

Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation

Crack control for substrate separation

Group III nitrides on nanopatterned substrates

High throughput epitaxial lift off for flexible electronics

Direct growth of lateral III-V bipolar transistor on silicon substrate

Direct growth of lateral III-V bipolar transistor on silicon substrate

CHENG CHENG-WEI

High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate

III-V field effect transistory (FET) and III-V semiconductor on insulator (IIIVOI) FET, integrated circuit (IC) chip and method of manufacture

Self-aligned III-V MOSFET diffusion regions and silicide-like alloy contact

High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate

Self-aligned III-V field effect transistor (FET), integrated circuit (IC) chip with self-aligned III-V FETS and method of manufacture

GLOBALFOUNDRIES INC

Multiple via structure and method

III-V lasers with integrated silicon photonic circuits

UNIV MICHIGAN

Methods of preparing flexible photovoltaic devices using epitaxial liftoff, and preserving the integrity of growth substrates used in epitaxial growth

FRANK MARTIN M

Controlling threshold voltage in carbon based field effect transistors

UNIV PRINCETON

Integrated photonic amplifier and detector

GUO DECHAO

FETs with hybrid channel materials

KIM JEEHWAN

Reduced S/D contact resistance of III-V MOSFET using low temperature metal-induced crystallization of n+ Ge

FOGEL KEITH E

Nanowires formed by employing solder nanodots