Inventor
FISCH MATTHEW A
US27 patents
Patents
27 patentsUS6208180B1Mar 27, 2001
Core clock correction in a 2/N mode clocking scheme
INTEL CORP181 citations98
US6006299ADec 21, 1999
Apparatus and method for caching lock conditions in a multi-processor system
INTEL CORP94 citations98
US5581782ADec 3, 1996
Computer system with distributed bus arbitration scheme for symmetric and priority agents
INTEL CORP117 citations98
US5774700AJun 30, 1998
Method and apparatus for determining the timing of snoop windows in a pipelined bus
INTEL CORP56 citations96
US5682516AOct 28, 1997
Computer system that maintains system wide cache coherency during deferred communication transactions
INTEL CORP58 citations96
US6668309B2Dec 23, 2003
Snoop blocking for cache coherency
INTEL CORP48 citations95
US6578116B2Jun 10, 2003
Snoop blocking for cache coherency
INTEL CORP18 citations92
US6268749B1Jul 31, 2001
Core clock correction in a 2/n mode clocking scheme
INTEL CORP28 citations92
US6216208B1Apr 10, 2001
Prefetch queue responsive to read request sequences
INTEL CORP39 citations92
US6078981AJun 20, 2000
Transaction stall technique to prevent livelock in multiple-processor systems
INTEL CORP33 citations92
US5909699AJun 1, 1999
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
INTEL CORP19 citations92
US5845107ADec 1, 1998
Signaling protocol conversion between a processor and a high-performance system bus
INTEL CORP36 citations92
US5802132ASep 1, 1998
Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
INTEL CORP33 citations92
US5797026AAug 18, 1998
Method and apparatus for self-snooping a bus during a boundary transaction
INTEL CORP41 citations92
US5764934AJun 9, 1998
Processor subsystem for use with a universal computer architecture
INTEL CORP41 citations92
US5572702ANov 5, 1996
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
INTEL CORP40 citations92
US5515516AMay 7, 1996
Initialization mechanism for symmetric arbitration agents
INTEL CORP22 citations92
US5535345AJul 9, 1996
Method and apparatus for sequencing misaligned external bus transactions in which the order of completion of corresponding split transaction requests is guaranteed
INTEL CORP43 citations88
US5784579AJul 21, 1998
Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth
INTEL CORP18 citations84
US5778441AJul 7, 1998
Method and apparatus for accessing split lock variables in a computer system
INTEL CORP18 citations84
US6460119B1Oct 1, 2002
Snoop blocking for cache coherency
INTEL CORP11 citations73
US6209068B1Mar 27, 2001
Read line buffer and signaling protocol for processor
INTEL CORP12 citations73
US6114887ASep 5, 2000
Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
INTEL CORP10 citations73
US5901297AMay 4, 1999
Initialization mechanism for symmetric arbitration agents
INTEL CORP9 citations73
US5896513AApr 20, 1999
Computer system providing a universal architecture adaptive to a variety of processor types and bus protocols
INTEL CORP14 citations73
US5834956ANov 10, 1998
Core clock correction in a 2/N mode clocking scheme
INTEL CORP11 citations73
US5826067AOct 20, 1998
Method and apparatus for preventing logic glitches in a 2/n clocking scheme
INTEL CORP9 citations73