Inventor
STORINO SALVATORE N
US17 patents
⚠️ This page may combine multiple inventors who share the name “STORINO SALVATORE N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
16 patentsUS6748556B1Jun 8, 2004
Changing the thread capacity of a multithreaded computer processor
IBM118 citations97
US6681345B1Jan 20, 2004
Field protection against thread loss in a multithreaded computer processor
IBM103 citations97
US6188247B1Feb 13, 2001
Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements
IBM56 citations92
US6163173ADec 19, 2000
Method and apparatus for implementing adjustable logic threshold in dynamic circuits for maximizing circuit performance
IBM19 citations84
US6150869ANov 21, 2000
Method and apparatus for body control in silicon-on-insulator (SOI) domino circuits
IBM17 citations82
US6094072AJul 25, 2000
Methods and apparatus for bipolar elimination in silicon-on-insulator (SOI) domino circuits
IBM15 citations71
US7142061B2Nov 28, 2006
Balanced single ended to differential signal converter
IBM3 citations62
US6084810AJul 4, 2000
Dynamic logic circuit with bitline repeater circuit
IBM4 citations62
US6462581B1Oct 8, 2002
Programmable timing boundary in dynamic circuits
IBM6 citations61
US6365934B1Apr 2, 2002
Method and apparatus for elimination of parasitic bipolar action in complementary oxide semiconductor (CMOS) silicon on insulator (SOI) circuits
IBM2 citations61
US6278157B1Aug 21, 2001
Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements
IBM2 citations59
US6808998B2Oct 26, 2004
Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits
IBM0 citations51
US6266800B1Jul 24, 2001
System and method for eliminating effects of parasitic bipolar transistor action in dynamic logic using setup time determination
IBM1 citations51
US6271686B2Aug 7, 2001
Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits
IBM1 citations48
US7839715B2Nov 23, 2010
SerDes double rate bitline with interlock to block precharge capture
IBM0 citations41
US7489039B2Feb 10, 2009
Metal fill region of a semiconductor chip
IBM0 citations35