Inventor
TRAN THINH
US43 patents
⚠️ This page may combine multiple inventors who share the name “TRAN THINH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
PEER INC
16 patentsUS11966559B2Apr 23, 2024
Selection ring user interface
PEER INC1 citations72
US11783555B2Oct 10, 2023
System and method for transferring content from one virtual environment to another
PEER INC2 citations72
US11650712B2May 16, 2023
Selection ring user interface
PEER INC1 citations72
US11609676B2Mar 21, 2023
Orthogonal fabric user interface
PEER INC2 citations72
US12498839B2Dec 16, 2025
System and method for synchronization of multiple users to interact in a common virtual space
PEER INC0 citations62
US12114231B2Oct 8, 2024
Content notification using a multi-dimensional fabric interface
PEER INC0 citations62
US11880543B2Jan 23, 2024
System and method for using portal systems in augmented reality virtual environments
PEER INC0 citations62
US11822763B2Nov 21, 2023
System and method for synchronization of multiple user devices in common virtual spaces
PEER INC0 citations62
US11809677B2Nov 7, 2023
System and method for enabling control of cursor movement on an associated large screen using dynamic grid density of an associated mobile device
PEER INC1 citations62
US11770357B2Sep 26, 2023
Multi-blockchain proof-of-activity platform
PEER INC0 citations62
US11595787B2Feb 28, 2023
Content notification using a multi-dimensional fabric interface
PEER INC0 citations62
US11586337B2Feb 21, 2023
System and method for using portal systems in augmented reality virtual environments
PEER INC1 citations62
US11463397B2Oct 4, 2022
Multi-blockchain proof-of-activity platform
PEER INC0 citations62
US12579764B2Mar 17, 2026
Systems and method for enhanced portal systems in augmented reality virtual environments
PEER INC0 citations51
US11770686B2Sep 26, 2023
Accessing content using time, topic, and location to transition between display modes
PEER INC0 citations51
US11681427B1Jun 20, 2023
System and method for dynamically grouping and displaying a plurality of content
PEER INC0 citations51
CYPRESS SEMICONDUCTOR CORP
14 patentsUS7142477B1Nov 28, 2006
Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses
CYPRESS SEMICONDUCTOR CORP54 citations95
US7269772B1Sep 11, 2007
Method and apparatus for built-in self-test (BIST) of integrated circuit device
CYPRESS SEMICONDUCTOR CORP23 citations92
US8705310B2Apr 22, 2014
Access methods and circuits for memory devices having multiple banks
CYPRESS SEMICONDUCTOR CORP5 citations84
US8527802B1Sep 3, 2013
Memory device data latency circuits and methods
CYPRESS SEMICONDUCTOR CORP8 citations84
US7684257B1Mar 23, 2010
Area efficient and fast static random access memory circuit and method
CYPRESS SEMICONDUCTOR CORP12 citations83
US7535772B1May 19, 2009
Configurable data path architecture and clocking scheme
CYPRESS SEMICONDUCTOR CORP13 citations83
US7403446B1Jul 22, 2008
Single late-write for standard synchronous SRAMs
CYPRESS SEMICONDUCTOR CORP10 citations83
US7196925B1Mar 27, 2007
Memory array with current limiting device for preventing particle induced latch-up
CYPRESS SEMICONDUCTOR CORP11 citations80
US9666255B2May 30, 2017
Access methods and circuits for memory devices having multiple banks
CYPRESS SEMICONDUCTOR CORP2 citations73
US9455027B1Sep 27, 2016
Power management system for high traffic integrated circuit
CYPRESS SEMICONDUCTOR CORP6 citations73
US7719908B1May 18, 2010
Memory having read disturb test mode
CYPRESS SEMICONDUCTOR CORP4 citations62
US8040164B2Oct 18, 2011
Circuits and methods for programming integrated circuit input and output impedances
CYPRESS SEMICONDUCTOR CORP3 citations61
US8873264B1Oct 28, 2014
Data forwarding circuits and methods for memory devices with write latency
CYPRESS SEMICONDUCTOR CORP0 citations52
US8358557B2Jan 22, 2013
Memory device and method
CYPRESS SEMICONDUCTOR CORP0 citations52
AVALANCHE TECHNOLOGY INC
4 patentsUS11211107B1Dec 28, 2021
Magnetic memory read circuit and calibration method therefor
AVALANCHE TECHNOLOGY INC3 citations73
US11854591B2Dec 26, 2023
Magnetic memory read circuit and calibration method therefor
AVALANCHE TECHNOLOGY INC0 citations62
US11289142B2Mar 29, 2022
Nonvolatile memory sensing circuit including variable current source
AVALANCHE TECHNOLOGY INC1 citations62
US10818330B2Oct 27, 2020
Fast programming of magnetic random access memory (MRAM)
AVALANCHE TECHNOLOGY INC0 citations42