Inventor

LINDERT NICK

US43 patents

⚠️ This page may combine multiple inventors who share the name “LINDERT NICK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LINDERT NICK

INTEL CORP

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Epitaxially deposited source/drain

Controlled faceting of source/drain regions

Metal gate transistors with epitaxial source and drain regions

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Method of forming abrupt source drain metal gate transistors

Pre-etch implantation damage for the removal of thin film layers

Penetrating implant for forming a semiconductor device

Fabricating strained channel epitaxial source/drain transistors

Plasma implantation of impurities in junction region recesses

Fabricating strained channel epitaxial source/drain transistors

Method for making a semiconductor device having an ultra-thin high-k gate dielectric

Self-aligned build-up of topographic features

Transistor device with gate control layer undercutting the gate dielectric

Technique for filling high aspect ratio, narrow structures with multiple metal layers and associated configurations

Creating shallow junction transistors

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls

Ultra-thin gate dielectrics

Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow

Common plate capacitor array connections, and processes of making same

Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material

Dual self-aligned gate endcap (SAGE) architectures

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls

Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material

Dual self-aligned gate endcap (SAGE) architectures

Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby

Cost effective precision resistor using blocked DEPOP method in self-aligned gate endcap (SAGE) architecture

Embedded memory device having MIM capacitor formed in excavated structure

Metal gate transistors with raised source and drain regions formed on heavily doped substrate

Forming abrupt source drain metal gate transistors

Plasma implantated impurities in junction region recesses

LINDERT NICK

Metal-insulator-metal (MIM) capacitor with insulator stack having a plurality of metal oxide layers

Formation of DRAM capacitor among metal interconnect

Rectangular capacitors for dynamic random access (DRAM) and dual-pass lithography methods to form the same

Capacitor with recessed plate portion for dynamic random access memory (DRAM) and method to form the same

Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer

CURELLO GIUSEPPE

Penetrating implant for forming a semiconductor device

Penetrating implant for forming a semiconductor device

UNIV CALIFORNIA

Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

WANG YIH

6F2 DRAM cell

STEIGERWALD JOSEPH M

Methods to form memory devices having a capacitor with a recessed electrode

KEATING STEVEN J

Embedded memory device having MIM capacitor formed in excavated structure