Inventor

VENIGALLA RAJASEKHAR

US83 patents

⚠️ This page may combine multiple inventors who share the name “VENIGALLA RAJASEKHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VENIGALLA RAJASEKHAR

IBM

Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess etch

Vertical FETs with variable bottom spacer recess

Vertical transistor fabrication and devices

Vertical field effect transistor with subway etch replacement metal gate

Vertical field effect transistors with metallic source/drain regions

Cutting fins and gates in CMOS devices

Gate cut with integrated etch stop layer

Vertical FETs with variable bottom spacer recess

Silicide contacts having different shapes on regions of a semiconductor device

Ceria-based polish processes, and ceria-based slurries

Vertical FETS with variable bottom spacer recess

Nanosheet field effect transistors with partial inside spacers

Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess ETCH

Three-dimensional stacked junctionless channels for dense SRAM

Vertical transistor fabrication and devices

Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices

Vertical transistor fabrication and devices

Vertical fin field effect transistor with air gap spacers

Vertical field effect transistors having epitaxial fin channel with spacers below gate structure

Integrated multiple gate length semiconductor device including self-aligned contacts

Fabricating tapered semiconductor devices

Gate cut with integrated etch stop layer

Nanosheet field effect transistors with partial inside spacers

Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction

Vertical FET devices with multiple channel lengths

Vertical fin field effect transistor with air gap spacers

Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices

Vertical fin field effect transistor with air gap spacers

Three-dimensional stacked junctionless channels for dense SRAM

Vertical field effect transistors with protective fin liner during bottom spacer recess etch

Vertical field effect transistors with metallic source/drain regions

Vertical transistor fabrication and devices

Additive core subtractive liner for metal cut etch processes

Subtractive vFET process flow with replacement metal gate and metallic source/drain

Shallow trench isolation structures and contact patterning

Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices

Vertical FETS with variable bottom spacer recess

Additive core subtractive liner for metal cut etch processes

MICRON TECHNOLOGY INC

Low resistance crosspoint architecture

Socket design for a memory device

Socket design for a memory device

Socket design for a memory device

TESSERA LLC

Gate cut with integrated etch stop layer

Gate cut with integrated etch stop layer

Gate cut with integrated etch stop layer

TESSERA INC

Nanosheet field effect transistors with partial inside spacers

Gate cut with integrated etch stop layer

ALPTEKIN EMRE

Method of forming silicide contacts of different shapes selectively on regions of a semiconductor device

UTOMO HENRY K

Structure and method for replacement metal gate field effect transistors

GLOBALFOUNDRIES INC

Integrated multiple gate length semiconductor device including self-aligned contacts