Inventor
BHATI ISHWAR S
IN2 patents
Patents
2 patentsUS10331582B2Jun 25, 2019
Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time
INTEL CORP2 citations70
US10866902B2Dec 15, 2020
Memory aware reordered source
INTEL CORP1 citations59