Inventor

DRAGONE SILVIO

CH69 patents

⚠️ This page may combine multiple inventors who share the name “DRAGONE SILVIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DRAGONE SILVIO

IBM

Tamper-respondent assemblies with enclosure-to-board protection

Tamper-respondent assemblies with enclosure-to-board protection

Tamper-respondent assemblies with enclosure-to-board protection

Tamper-proof electronic packages with stressed glass component substrate(s)

Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration

System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration

Tamper-respondent assembly with sensor connection adapter

Vented tamper-respondent assemblies

Tamper-proof electronic packages with stressed glass component substrate(s)

Circuit boards and electronic packages with embedded tamper-respondent sensor

Tamper-respondent assemblies with enclosure-to-board protection

Circuit boards and electronic packages with embedded tamper-respondent sensor

Tamper-proof electronic packages formed with stressed glass

System and method utilizing programmable ordering relation for direct memory access

Circuit boards and electronic packages with embedded tamper-respondent sensor

Circuit boards and electronic packages with embedded tamper-respondent sensor

Tamper-respondent assembly with flexible tamper-detect sensor(s) overlying in-situ-formed tamper-detect sensor

Tamper-respondent assemblies with in situ vent structure(s)

Tamper-proof electronic packages formed with stressed glass

Electronic devices with individual security circuits

Data detection mitigation in printed circuit boards

Hardware security modules for executing zero-knowledge proofs

Method for detecting cliques in graphs

Iterative refinement apparatus

Secure ventilation through protective flexible sensors

Tamper-respondent sensors with liquid crystal polymer layers

Reducing impact of context switches through dynamic memory-mapping overallocation

Enclosure with tamper respondent sensor

Synchronizing requests to access computing resources

Radio-assisted tamper protection of hardware

Secure signal integrity

Circuitized structure with 3-dimensional configuration

Electronic devices with individual security circuits

Multi-level security enforcement

Coupling a general purpose processor to an application specific instruction set processor

Coupling GP processor with reserved instruction interface via coprocessor port with operation data flow to application specific ISA processor with translation pre-decoder

Detecting a timeout of elements in an element processing system

Quantum safe key exchange scheme

Quantum safe key exchange scheme

Priority-arbitrated access to a set of one or more computational engines

Enclosure with tamper respondent sensor

Key attribute verification

Controlling operation of multiple computational engines

Electronic devices with individual security circuits

Secure signal integrity

Synchronizing requests to access computing resources

Vented tamper-respondent assemblies

Synchronizing write operations

CONDORELLI VINCENZO

Configurable integrated tamper detection circuitry

DRAGONE SILVIO

Providing nondeterministic data