Inventor

MEALEY BRUCE

US52 patents

⚠️ This page may combine multiple inventors who share the name “MEALEY BRUCE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEALEY BRUCE

IBM

Virtual logical partition terminal

Techniques for escalating interrupts in a data processing system to a higher software stack level

Enabling poll/select style interfaces with coherent accelerators

Enabling poll/select style interfaces with coherent accelerators

Method, system, and program for transferring data directed to virtual memory addresses to a device memory

Method, apparatus, and computer program product for migrating data subject to access by input/output devices

Dynamic virtual processor manager

Sharing an accelerator context across multiple processes

Key-controlled object-based memory protection

Emulating memory mapped I/O for coherent accelerators in error state

Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core

Dynamic virtual processor manager

Memory page de-duplication in a computer system that includes a plurality of virtual machines

Memory page de-duplication in a computer system that includes a plurality of virtual machines

Kernel error recovery disablement and shared recovery routine footprint areas

Recovery routine masking and barriers to support phased recovery development

Key-controlled object-based memory protection

Method and system for system performance optimization via heuristically optimized buses

Efficient critical thread scheduling for non-privileged thread requests

Efficient critical thread scheduling for non privileged thread requests

Efficient critical thread scheduling for non-privileged thread requests

Using a dual mode reader writer lock

Affinity-aware parallel zeroing of memory in non-uniform memory access (NUMA) servers

Off-line affinity-aware parallel zeroing of memory in non-uniform memory access (NUMA) servers

Accelerator access control

Scaling address space utilization in a multi-threaded, multi-processor computer

Accelerator access control

Detecting illegal reuse of memory with low resource impact

Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core

Off-line affinity-aware parallel zeroing of memory in non-uniform memory access (NUMA) servers

Affinity aware parallel zeroing of memory in non-uniform memory access (NUMA) servers

Resolving page faults out of context

Affinity-aware parallel zeroing of pages in non-uniform memory access (NUMA) servers

Sharing an accelerator context across multiple processes

Resolving page faults out of context for shared contexts

Efficient critical thread scheduling for non-privileged thread requests

Low latency scheduling on simultaneous multi-threading cores

Low latency scheduling on simultaneous multi-threading cores

Key-controlled object-based memory protection

Affinity-aware parallel zeroing of memory for initialization of large pages in non-uniform memory access (NUMA) servers

Affinity-aware parallel zeroing of memory for initialization of large pages in non-uniform memory access (NUMA) servers

Affinity-aware parallel zeroing of memory for initialization of large pages in non-uniform memory access (NUMA) servers

Shared and exclusive accelerator access

Scaling address space utilization in a multi-threaded, multi-processor computer

MEALEY BRUCE

Using a dual mode reader writer lock

Dual mode reader writer lock

Dual mode reader writer lock

ANAND VAIJAYANTHIMALA K

Controlling priority of multi-threaded hardware resources by system calls

LYONS MICHAEL E

Software component self-scrubbing

MALL MICHAEL GERARD

Global and local counts for efficient memory page pinning in a multiprocessor system