Inventor

WOLRICH GILBERT M

US156 patents

⚠️ This page may combine multiple inventors who share the name “WOLRICH GILBERT M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WOLRICH GILBERT M

INTEL CORP

Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction

Multi-threaded sequenced receive for fast network port stream of packets

Look-ahead hash chain matching for data compression

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Supporting data compression using match scoring

Instruction and logic to provide SIMD secure hashing round slice functionality

Multi-threaded sequenced receive for fast network port stream of packets

Hardware accelerator

System and method for cryptography processing units and multiplier

Instruction and logic to provide SIMD secure hashing round slice functionality

SM3 hash function message expansion processors, methods, systems, and instructions

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Look-ahead hash chain matching for data compression

Instructions and logic to provide SIMD SM3 cryptographic hashing functionality

Heterogeneous compression architecture for optimized compression ratio

Method and apparatus for performing a shift and exclusive or operation in a single instruction

Partitioned data compression using accelerator

SMS4 acceleration processors, methods, systems, and instructions

Instructions processors, methods, and systems to process secure hash algorithms

Instructions processors, methods, and systems to process secure hash algorithms

Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit

Method and apparatus for performing an authentication after cipher operation in a network processor

Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor

Processor having content addressable memory for block-based queue structures

Folding for a multi-threaded network processor

Apparatus and method for generating a Galois-field syndrome

GOPAL VINODH

Matrix multiply accumulate instruction

SIMD integer multiply-accumulate instruction for multi-precision arithmetic

Filter for network intrusion and virus detection

Method and apparatus for performing a shift and exclusive or operation in a single instruction

Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage

Systems, methods, and apparatuses for compression using hardware and software

Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction

Apparatus and method to accelerate compression and decompression operations

Add instructions to add three source operands

DIGITAL EQUIPMENT CORP

State machine phase lock loop

Mechanism for high bandwidth DMA transfers in a PCI environment

Digital computer system with cache controller coordinating both vector and scalar operations

Mechanism for high bandwidth DMA transfers in a PCI environment

Multiply pipe round adder

Rounding adder for floating point processor

Floating point unit data path alignment

Reduced-latency floating-point pipeline using normalization shifts of both operands

YAP KIRK S

Method and apparatus to process KECCAK secure hashing algorithm

Method and apparatus to process SHA-2 secure hashing algorithm

FEGHALI WAJDI K

Cryptographic system, method and multiplier

WOLRICH GILBERT M

Instruction set for message scheduling of SHA256 algorithm