Inventor
CHOU ANTHONY I-CHIH
US9 patents
⚠️ This page may combine multiple inventors who share the name “CHOU ANTHONY I-CHIH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
6 patentsUS6821833B1Nov 23, 2004
Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby
IBM46 citations92
US7160771B2Jan 9, 2007
Forming gate oxides having multiple thicknesses
IBM20 citations88
US7456115B2Nov 25, 2008
Method for forming semiconductor devices having reduced gate edge leakage current
IBM8 citations73
US8343781B2Jan 1, 2013
Electrical mask inspection
IBM6 citations72
US9401325B2Jul 26, 2016
Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication
IBM0 citations52
US8829616B2Sep 9, 2014
Method and structure for body contacted FET with reduced body resistance and source to drain contact leakage
IBM0 citations41
GLOBALFOUNDRIES INC
2 patentsUS9269786B2Feb 23, 2016
Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors
GLOBALFOUNDRIES INC13 citations84
US9595518B1Mar 14, 2017
Fin-type metal-semiconductor resistors and fabrication methods thereof
GLOBALFOUNDRIES INC10 citations82