Inventor

YAMASHITA TENKO

US557 patents

⚠️ This page may combine multiple inventors who share the name “YAMASHITA TENKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YAMASHITA TENKO

IBM

Air gap spacer formation for nano-scale semiconductor devices

Inner spacer for nanosheet transistors

Air gap spacer formation for nano-scale semiconductor devices

Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain

Fabrication of vertical field effect transistor structure with controlled gate length

Etch stop for airgap protection

MOSFET with asymmetric self-aligned contact

Method and structure of forming controllable unmerged epitaxial material

Method and structure for improving finFET with epitaxy source/drain

Stacked nanowire field effect transistor

Buried power and ground in stacked vertical transport field effect transistors

Stacked vertical NFET and PFET

Uniform bottom spacers in vertical field effect transistors

Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors

Nanosheet transistors having thin and thick gate dielectric material

Forming air-gap spacer for vertical field effect transistor

Forming vertical and horizontal field effect transistors on the same substrate

Interlayer via

Asymmetric multi-gate finFET

Semiconductor device including finFET and fin varactor

Semiconductor device including self-aligned gate structure and improved gate spacer topography

Forming strained and relaxed silicon and silicon germanium fins on the same wafer

Forming vertical transistors and metal-insulator-metal capacitors on the same chip

Split fin field effect transistor enabling back bias on fin type field effect transistors

Self aligned epitaxial based punch through control

Pure boron for silicide contact

Nanowire semiconductor device including lateral-etch barrier region

Stacked nanowire device width adjustment by gas cluster ion beam (GCIB)

Fin cut on SIT level

Independent gate vertical FinFET structure

Dual epitaxial process including spacer adjustment

Bulk fin-field effect transistors with well defined isolation

Fin isolation in multi-gate field effect transistors

Bulk fin-field effect transistors with well defined isolation

Strained silicon nFET and silicon germanium pFET on same wafer

Preventing Fin erosion and limiting EPI overburden in FinFET structures by composite hardmask

Preventing FIN erosion and limiting Epi overburden in FinFET structures by composite hardmask

GLOBALFOUNDRIES INC

Stacked nanosheet field-effect transistor with air gap spacers

Method of forming vertical field effect transistors with different gate lengths and a resulting structure

Nanosheet devices with CMOS epitaxy and method of forming

Vertical transistor having buried contact, and contacts using work function metals and silicides

Air gap adjacent a bottom source/drain region of vertical transistor device

Methods of forming vertical transistor devices with different effective gate lengths

BASKER VEERARAGHAVAN S

Cut-very-last dual-epi flow

SOI FinFET with recessed merged Fins and liner for enhanced stress coupling

Finfet with reduced parasitic capacitance

ANDO TAKASHI

FinFET parasitic capacitance reduction using air gap

FinFET parasitic capacitance reduction using air gap

CHENG KANGGUO

Bulk fin-field effect transistors with well defined isolation

GLOBALFOUNDRIES US 2 LLC

Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides