Inventor
MEIL GAVIN B
US21 patents
Patents
21 patentsUS9251304B2Feb 2, 2016
Circuit design evaluation with compact multi-waveform representations
IBM17 citations92
US10331822B2Jun 25, 2019
Clock-gating phase algebra for clock analysis
IBM2 citations83
US10325041B2Jun 18, 2019
Circuit design analyzer
IBM2 citations83
US10325040B2Jun 18, 2019
Conditional phase algebra for clock analysis
IBM2 citations83
US10216881B2Feb 26, 2019
Phase algebra for analysis of hierarchical designs
IBM6 citations83
US9916407B2Mar 13, 2018
Phase algebra for analysis of hierarchical designs
IBM9 citations83
US9798844B2Oct 24, 2017
Phase algebra for analysis of hierarchical designs
IBM7 citations83
US9547732B2Jan 17, 2017
Static checking of asynchronous clock domain crossings
IBM3 citations83
US9268889B2Feb 23, 2016
Verification of asynchronous clock domain crossings
IBM3 citations83
US10990725B2Apr 27, 2021
Clock-gating phase algebra for clock analysis
IBM0 citations62
US10599792B2Mar 24, 2020
Circuit design analyzer
IBM0 citations51
US10558782B2Feb 11, 2020
Phase algebra for virtual clock and mode extraction in hierarchical designs
IBM0 citations51
US10552558B2Feb 4, 2020
Conditional phase algebra for clock analysis
IBM0 citations51
US10552559B2Feb 4, 2020
Glitch-aware phase algebra for clock analysis
IBM0 citations51
US10515164B2Dec 24, 2019
Clock-gating phase algebra for clock analysis
IBM0 citations51
US10318695B2Jun 11, 2019
Phase algebra for virtual clock and mode extraction in hierarchical designs
IBM0 citations51
US9830412B2Nov 28, 2017
Glitch-aware phase algebra for clock analysis
IBM0 citations51
US9536024B2Jan 3, 2017
Methods for static checking of asynchronous clock domain crossings
IBM0 citations51
US11907634B2Feb 20, 2024
Automating addition of power supply rails, fences, and level translators to a modular circuit design
IBM0 citations41
US10503856B2Dec 10, 2019
Phase algebra for specifying clocks and modes in hierarchical designs
IBM0 citations41
US10031987B2Jul 24, 2018
Verification of untimed nets
IBM0 citations41