Inventor

FUJIWARA HIDEHIRO

TW149 patents

⚠️ This page may combine multiple inventors who share the name “FUJIWARA HIDEHIRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FUJIWARA HIDEHIRO

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of forming semiconductor device including distributed write driving arrangement

Voltage regulator with power rail tracking

Method and system to balance ground bounce

Memory cell and method of manufacturing the same

Semiconductor device including distributed write driving arrangement and method of operating same

Memory computation circuit and method

Semiconductor device including distributed write driving arrangement and method of operating same

Static random access memory with write assist circuit

SRAM cell word line structure with reduced RC effects

Semiconductor device having buried metal line and fabrication method of the same

Memory read stability enhancement with short segmented bit line architecture

SRAM cell for interleaved wordline scheme

Layout design for manufacturing a memory cell

Method of certifying safety levels of semiconductor memories in integrated circuits

Memory array circuit and method of manufacturing same

4CPP SRAM cell and array

Voltage regulator with power rail tracking

Memory macro including through-silicon via

Semiconductor device including distributed write driving arrangement

Systems and methods for memory operation using local word lines

Method and system to balance ground bounce

Memory array circuit and method of manufacturing same

Bitcell supporting bit-write-mask function

Voltage regulator with power rail tracking

Four CPP wide memory cell with buried power grid, and method of fabricating same

Memory macro including through-silicon via

Systems and methods for memory operation using local word lines

Bitcell supporting bit-write-mask function

4Cpp SRAM cell and array

Mixed threshold voltage memory array

Boost bypass circuitry in a memory storage device

SRAM cell for interleaved wordline scheme

Memory cell

Memory read stability enhancement with short segmented bit line architecture

SRAM cell for interleaved wordline scheme

Layout design for manufacturing a memory cell

Memory circuit having shared word line

Memory read stability enhancement with short segmented bit line architecture

Memory with write assist circuit

Memory device including a word line with portions with different sizes in different metal layers

Header layout design including backside power rail

RENESAS ELECTRONICS CORP

Semiconductor integrated circuit device

Semiconductor integrated circuit device

Semiconductor integrated circuit device

Semiconductor device including negative bias voltage generation circuit

Semiconductor integrated circuit device

Semiconductor integrated circuit device

TAIWAN SEMICONDUCTOR MFG

Static random access memory with assist circuit

Multi-port memory cell

FUJIWARA HIDEHIRO

Semiconductor device