Inventor
Kucharski Cliff
US23 patents
Patents
23 patentsUS10073699B2Sep 11, 2018
Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture
IBM5 citations73
US9747217B2Aug 29, 2017
Distributed history buffer flush and restore handling in a parallel slice design
IBM3 citations73
US9740620B2Aug 22, 2017
Distributed history buffer flush and restore handling in a parallel slice design
IBM5 citations73
US9639418B2May 2, 2017
Parity protection of a register
IBM4 citations72
US11941398B1Mar 26, 2024
Fast mapper restore for flush in processor
IBM1 citations62
US11768684B2Sep 26, 2023
Compaction of architected registers in a simultaneous multithreading processor
IBM0 citations62
US11138050B2Oct 5, 2021
Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
IBM0 citations62
US11093282B2Aug 17, 2021
Register file write using pointers
IBM0 citations62
US10255071B2Apr 9, 2019
Method and apparatus for managing a speculative transaction in a processing unit
IBM1 citations62
US11194578B2Dec 7, 2021
Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor
IBM0 citations61
US11144364B2Oct 12, 2021
Supporting speculative microprocessor instruction execution
IBM1 citations60
US10949205B2Mar 16, 2021
Implementation of execution compression of instructions in slice target register file mapper
IBM1 citations58
US11561794B2Jan 24, 2023
Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry
IBM0 citations52
US10282205B2May 7, 2019
Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions
IBM0 citations52
US10248421B2Apr 2, 2019
Operation of a multi-slice processor with reduced flush and restore latency
IBM0 citations52
US10241790B2Mar 26, 2019
Operation of a multi-slice processor with reduced flush and restore latency
IBM0 citations52
US11188332B2Nov 30, 2021
System and handling of register data in processors
IBM0 citations51
US10649779B2May 12, 2020
Variable latency pipe for interleaving instruction tags in a microprocessor
IBM0 citations51
US10613868B2Apr 7, 2020
Variable latency pipe for interleaving instruction tags in a microprocessor
IBM0 citations51
US10489253B2Nov 26, 2019
On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor
IBM0 citations51
US10318356B2Jun 11, 2019
Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
IBM0 citations51
US11030018B2Jun 8, 2021
On-demand multi-tiered hang buster for SMT microprocessor
IBM0 citations49
US10289415B2May 14, 2019
Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data
IBM0 citations41