Inventor

NASRULLAH JAWAD

US21 patents

⚠️ This page may combine multiple inventors who share the name “NASRULLAH JAWAD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NASRULLAH JAWAD

INTEL CORP

Method and apparatus for managing a spin transfer torque memory

Method and systems for energy efficiency and energy conservation including on-off keying for power control

Apparatus and method for reduced core entry into a power state having a powered down core cache

Controlling power consumption of a processor using interrupt-mediated on-off keying

Apparatus and method for flushing dirty cache lines based on cache activity levels

Controlling processor consumption using on-off keying having a maxiumum off time

Controlling processor consumption using on-off keying having a maximum off time

Block-level sleep logic

SHENZHEN CHIPULLER CHIP TECH CO LTD

Over-the-air hardware update

Over-the-air hardware update

Method and apparatus to use active semiconductor interposers for RF signal chain in modular stacked integrated circuits

Method and apparatus to use active semiconductor interposers for RF signal chain in modular stacked integrated circuits

Assembly of flexible and integrated module packages with leadframes

BURR JAMES B

Raised source/drain with super steep retrograde channel

Formation of a super steep retrograde channel

Formation of a super steep retrograde channel

NASRULLAH JAWAD

Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states

Method and systems for energy efficiency and energy conservation including on-off keying for power control

INNOVATIVE SEMICONDUCTORS

System and method for dynamic impedance matching

ZGLUE INC

System and methods for producing modular stacked integrated circuits

WILKERSON CHRISTOPHER

Semiconductor chip with adaptive BIST cache testing during runtime