Inventor

PARNELL THOMAS

CH64 patents

⚠️ This page may combine multiple inventors who share the name “PARNELL THOMAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARNELL THOMAS

IBM

Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory

Mitigating read errors following programming in a multi-level non-volatile memory

Data deduplication with reduced hash computations

Recovery of multi-page failures in non-volatile memory system

Dynamically optimizing flash data retention or endurance based on data write frequency

State-dependent read voltage threshold adaptation for nonvolatile memory

Reducing read disturb effect on partially programmed blocks of non-volatile memory

Error-correction encoding and decoding

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Non-volatile memory data storage with low read amplification

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Extending useful life of a non-volatile memory by health grading

Determining prefix codes for pseudo-dynamic data compression utilizing clusters formed based on compression ratio

Device for selecting a level for at least one read voltage

Techniques for dynamically adjusting over-provisioning space of a flash controller based on workload characteristics

Non-binary context mixing compressor/decompressor

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Page-level health equalization

Selectively de-straddling data pages in non-volatile memory

Data packing for compression-enabled storage systems

Diagonal anti-diagonal memory structure

Adapting erase cycle parameters to promote endurance of a memory

Load-balancing training of recommender system for heterogeneous systems

Machine learning in heterogeneous processing systems

Straggler mitigation for iterative machine learning via task preemption

Data protection techniques for a non-volatile memory array

Updating prefix codes for pseudo-dynamic data compression

Parallel training of machine learning models

Accelerating decision tree inferences based on complementary tensor operation sets

Training decision tree-based predictive models

Joint execution of decision tree nodes for accelerating inferences

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

Diagonal anti-diagonal memory structure

Selectively de-straddling data pages in non-volatile memory

Reducing a decoding error floor by post-processing codewords encoded by binary symmetry-invariant product codes

Data deduplication with reduced hash computations

Initializing a pseudo-dynamic data compression system with predetermined history data typical of actual data

Estimation of level-thresholds for memory cells

Workload-adaptive data packing algorithm

Diagonal anti-diagonal memory structure

Multi-chip device and method for storing data

Error-correction encoding and decoding

Reducing read access latency by straddling pages across non-volatile memory channels

Efficient management of page retirement in non-volatile memory utilizing page retirement classes

Device and method for storing data in a plurality of multi-level cell memory chips

Data deduplication with reduced hash computations

Data packing for compression-enabled storage systems

Data encoding in solid-state storage devices

CATERPILLAR INC

Repaired pistons and collection thereof