Inventor

SURISETTY CHARAN V V S

US38 patents

⚠️ This page may combine multiple inventors who share the name “SURISETTY CHARAN V V S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SURISETTY CHARAN V V S

IBM

Co-integration of different fin pitches for logic and analog devices

Double diamond shaped unmerged epitaxy for tall fins in tight pitch

Method of forming contact useful in replacement metal gate processing and related semiconductor structure

Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

Method and structure of improving contact resistance for passive and long channel devices

Self-aligned local interconnect technology

Strained FinFET by epitaxial stressor independent of gate pitch

Simultaneously fabricating a high voltage transistor and a finFET

Semiconductor device with low-k gate cap and self-aligned contact

Method and structure of improving contact resistance for passive and long channel devices

Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

Simultaneously fabricating a high voltage transistor and a FinFET

Self-aligned local interconnect technology

Method and structure of improving contact resistance for passive and long channel devices

Spacer for trench epitaxial structures

Self-aligned low dielectric constant gate cap and a method of forming the same

Shallow trench isolation regions made from crystalline oxides

Method and structure of improving contact resistance for passive and long channel devices

FinFETs with high quality source/drain structures

Simultaneously fabricating a high voltage transistor and a finFET

Spacer for trench epitaxial structures

Spacer for trench epitaxial structures

FET trench dipole formation

Spacer for trench epitaxial structures

Forming spacer for trench epitaxial structures

Self-aligned local interconnect technology

Self-aligned low dielectric constant gate cap and a method of forming the same

Semiconductor device with low-K gate cap and self-aligned contact

FINFETs with high quality source/drain structures

FET trench dipole formation

Strained FinFET by epitaxial stressor independent of gate pitch

Contact resistance reduction for advanced technology nodes

Inter-level dielectric layer in replacement metal gates and resistor fabrication

TESSERA INC

Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack

ELPIS TECH INC

Simultaneously fabricating a high voltage transistor and a FinFET

Self-aligned low dielectric constant gate cap and a method of forming the same

GLOBALFOUNDRIES INC

Forming stressed epitaxial layers between gates separated by different pitches