Inventor

LU CHING-HUANG

US103 patents

⚠️ This page may combine multiple inventors who share the name “LU CHING-HUANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LU CHING-HUANG

SANDISK TECHNOLOGIES LLC

Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Suppressing program disturb during program recovery in memory device

Two-stage ramp up of word line voltages in memory device to suppress read disturb

Multi-pass programming with modified pass voltages to tighten threshold voltage distributions

Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors

Forming memory cell film in stack opening

Programming of dummy memory cell to reduce charge loss in select gate transistor

Reducing hot electron injection type of read disturb during read recovery phase in 3D memory

Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof

Pre-read voltage pulse for first read error handling

Three-dimensional memory device with drain-select-level isolation structures and method of making the same

Three-dimensional memory device with drain-select-level isolation structures and method of making the same

Detecting short circuit between word line and source line in memory device and recovery method

Memory device with channel discharge before program-verify based on data state and sub-block position

Three dimensional NAND memory device with drain select gate electrode shared between multiple strings

Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Memory device with compensation for erase speed variations due to blocking oxide layer thinning

Multi-pass programming process for memory device which omits verify test in first program pass

Three-dimensional memory devices using carbon-doped aluminum oxide backside blocking dielectric layer for etch resistivity enhancement and methods of making the same

Memory device with compensation for erase speed variations due to blocking oxide layer thinning

Multi-state programming in memory device with loop-dependent bit line voltage during verify

Memory device with compensation for program speed variations due to block oxide thinning

Adjusting voltage on adjacent word line during verify of memory cells on selected word line in multi-pass programming

Early ramp down of dummy word line voltage during read to suppress select gate transistor downshift

Electric field to reduce select gate threshold voltage shift

Charge storage region in non-volatile memory

Word line-dependent and temperature-dependent erase depth

Reducing neighboring word line in interference using low-k oxide

Method of fabricating 3D NAND

Method of forming memory cell film

Three-dimensional memory device with drain-select-level isolation structures and method of making the same

Read bias adjustment for compensating threshold voltage shift due to lateral charge movement

Multi-pass programming process for memory device which omits verify test in first program pass

Memory device with reduced neighbor word line interference using adjustable voltage on source-side unselected word line

SANDISK TECHNOLOGIES INC

Multi-tier replacement memory stack structure integration scheme

Fluorine-blocking insulating spacer for backside contact structure of three-dimensional memory structures

Charge redistribution during erase in charge trapping memory

Three-dimensional memory devices having a single layer channel and methods of making thereof

Programming memory with reduced short-term charge loss

Programming memory with reduced short-term charge loss

Method to recover cycling damage and improve long term data retention

Weak erase after programming to improve data retention in charge-trapping memory

Dummy word line control scheme for non-volatile memory

MICRON TECHNOLOGY INC

Adaptive time sense parameters and overdrive voltage parameters for wordlines at corner temperatures in a memory sub-system

Adaptive sensing time for memory operations

Memory read operation using a voltage pattern based on a read command type

SPANSION LLC

Non-volatile memory with silicided bit line contacts

Non-Volatile memory with silicided bit line contacts

YANG XIAOYU

Process for masking and removal of residue from complex shapes

WANG JINWEN

Method of forming a fully wrapped-around shielded PMR writer pole