Inventor
PAPADOPOULOU EVANTHIA
US16 patents
Patents
16 patentsUS6317859B1Nov 13, 2001
Method and system for determining critical area for circuit layouts
IBM168 citations98
US6178539B1Jan 23, 2001
Method and system for determining critical area for circuit layouts using voronoi diagrams
IBM87 citations96
US6247853B1Jun 19, 2001
Incremental method for critical area and critical region computation of via blocks
IBM100 citations95
US7143371B2Nov 28, 2006
Critical area computation of composite fault mechanisms using voronoi diagrams
IBM16 citations91
US6044208AMar 28, 2000
Incremental critical area computation for VLSI yield prediction
IBM40 citations91
US7404164B2Jul 22, 2008
IC design modeling allowing dimension-dependent rule checking
IBM10 citations83
US7240306B2Jul 3, 2007
Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing
IBM8 citations71
US7703061B2Apr 20, 2010
IC design modeling allowing dimension-dependent rule checking
IBM2 citations62
US7685553B2Mar 23, 2010
System and method for global circuit routing incorporating estimation of critical area estimate metrics
IBM2 citations62
US7555735B2Jun 30, 2009
IC design modeling allowing dimension-dependent rule checking
IBM1 citations62
US7404159B2Jul 22, 2008
Critical area computation of composite fault mechanisms using Voronoi diagrams
IBM4 citations61
US7661080B2Feb 9, 2010
Method and apparatus for net-aware critical area extraction
IBM4 citations56
US7752580B2Jul 6, 2010
Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique
IBM0 citations51
US7752589B2Jul 6, 2010
Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design
IBM0 citations51
US7577927B2Aug 18, 2009
IC design modeling allowing dimension-dependent rule checking
IBM0 citations51
US7810060B2Oct 5, 2010
Critical area computation of composite fault mechanisms using Voronoi diagrams
IBM0 citations44