Inventor

XIONG WEIZE

US16 patents

⚠️ This page may combine multiple inventors who share the name “XIONG WEIZE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TEXAS INSTRUMENTS INC

10 patents

US7683417B2Mar 23, 2010

Memory device with memory cell including MuGFET and fin capacitor

TEXAS INSTRUMENTS INC25 citations91

US7094650B2Aug 22, 2006

Gate electrode for FinFET device

TEXAS INSTRUMENTS INC20 citations91

US7939393B2May 10, 2011

Method of adjusting FDSOI threshold voltage through oxide charges generation in the buried oxide

TEXAS INSTRUMENTS INC8 citations83

US7238567B2Jul 3, 2007

System and method for integrating low schottky barrier metal source/drain

TEXAS INSTRUMENTS INC12 citations83

US7897994B2Mar 1, 2011

Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate

TEXAS INSTRUMENTS INC1 citations62

US7253043B2Aug 7, 2007

Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate

TEXAS INSTRUMENTS INC0 citations41

XIONG WEIZE

5 patents

US8114727B2Feb 14, 2012

Disposable spacer integration with stress memorization technique and silicon-germanium

XIONG WEIZE10 citations83

US8138035B2Mar 20, 2012

Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels

XIONG WEIZE7 citations82

US8470707B2Jun 25, 2013

Silicide method

XIONG WEIZE2 citations61

US8410519B2Apr 2, 2013

Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels

XIONG WEIZE1 citations61

US8067792B2Nov 29, 2011

Memory device with memory cell including MuGFET and FIN capacitor

XIONG WEIZE1 citations50

TIGELAAR HOWARD

1 patent

US8581317B2Nov 12, 2013

SOI MuGFETs having single gate electrode level

TIGELAAR HOWARD1 citations45

XIONG WEIZE

TEXAS INSTRUMENTS INC

Memory device with memory cell including MuGFET and fin capacitor

Gate electrode for FinFET device

Method of adjusting FDSOI threshold voltage through oxide charges generation in the buried oxide

System and method for integrating low schottky barrier metal source/drain

Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate

Short channel semiconductor device fabrication

CMOS integration method for optimal IO transistor VT

Dual metal gates for mugfet device

Multiple-gate MOSFET device and associated manufacturing methods

Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a DSB substrate

XIONG WEIZE

Disposable spacer integration with stress memorization technique and silicon-germanium

Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels

Silicide method

Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels

Memory device with memory cell including MuGFET and FIN capacitor

TIGELAAR HOWARD

SOI MuGFETs having single gate electrode level