Inventor
OKUNO MICHITAKA
JP23 patents
⚠️ This page may combine multiple inventors who share the name “OKUNO MICHITAKA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HITACHI LTD
11 patentsUS7656887B2Feb 2, 2010
Traffic control method for network equipment
HITACHI LTD9 citations83
US7630373B2Dec 8, 2009
Packet transfer apparatus
HITACHI LTD14 citations83
US9600380B2Mar 21, 2017
Failure recovery system and method of creating the failure recovery system
HITACHI LTD6 citations73
US8868998B2Oct 21, 2014
Packet communication apparatus and packet communication method
HITACHI LTD4 citations73
US9769265B2Sep 19, 2017
Communication system, management computer, and session information migration method
HITACHI LTD2 citations71
US8380065B2Feb 19, 2013
Optical access system and optical line terminal
HITACHI LTD4 citations63
US7440457B2Oct 21, 2008
Network-processor accelerator
HITACHI LTD6 citations62
US7529251B2May 5, 2009
Data transfer device
HITACHI LTD2 citations61
US9535730B2Jan 3, 2017
Communication apparatus and configuration method
HITACHI LTD0 citations42
US9521056B2Dec 13, 2016
Communication system
HITACHI LTD0 citations41
US9407459B2Aug 2, 2016
Communication apparatus, communication system, and communication method to transmit and receive Ethernet frames
HITACHI LTD0 citations40
OKUNO MICHITAKA
5 patentsUS9294342B2Mar 22, 2016
Network node apparatus system, apparatus, and method
OKUNO MICHITAKA3 citations72
US8135004B2Mar 13, 2012
Multi-plane cell switch fabric system
OKUNO MICHITAKA2 citations61
US8798051B2Aug 5, 2014
Information and communication processing system, method, and network node
OKUNO MICHITAKA2 citations60
US8782239B2Jul 15, 2014
Distributed router computing at network nodes
OKUNO MICHITAKA2 citations60
US8116305B2Feb 14, 2012
Multi-plane cell switch fabric system
OKUNO MICHITAKA0 citations40
IBM
4 patentsUS7051177B2May 23, 2006
Method for measuring memory latency in a hierarchical memory system
IBM11 citations83
US7047398B2May 16, 2006
Analyzing instruction completion delays in a processor
IBM19 citations83
US6970999B2Nov 29, 2005
Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters
IBM13 citations83
US6910120B2Jun 21, 2005
Speculative counting of performance events with rewind counter
IBM9 citations73