Inventor
SURA ZEHRA N
US29 patents
⚠️ This page may combine multiple inventors who share the name “SURA ZEHRA N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS9513828B2Dec 6, 2016
Accessing global data from accelerator devices
IBM36 citations92
US9563428B2Feb 7, 2017
Schedulers with load-store queue awareness
IBM13 citations83
US10223260B2Mar 5, 2019
Compiler-generated memory mapping hints
IBM2 citations73
US11687369B2Jun 27, 2023
Flexible optimized data handling in systems with multiple memories
IBM1 citations62
US11416548B2Aug 16, 2022
Index management for a database
IBM1 citations62
US10996989B2May 4, 2021
Flexible optimized data handling in systems with multiple memories
IBM1 citations62
US8055849B2Nov 8, 2011
Reducing cache pollution of a software controlled cache
IBM4 citations62
US7784037B2Aug 24, 2010
Compiler implemented software cache method in which non-aliased explicitly fetched data are excluded
IBM5 citations61
US9229715B2Jan 5, 2016
Method and apparatus for efficient inter-thread synchronization for helper threads
IBM0 citations52
US9183063B2Nov 10, 2015
Power-constrained compiler code generation and scheduling of work in a heterogeneous processing system
IBM0 citations52
US9110734B2Aug 18, 2015
Power-constrained compiler code generation and scheduling of work in a heterogeneous processing system
IBM0 citations52
US9772825B2Sep 26, 2017
Program structure-based blocking
IBM0 citations51
US9772824B2Sep 26, 2017
Program structure-based blocking
IBM0 citations51
US9552196B2Jan 24, 2017
Schedulers with load-store queue awareness
IBM0 citations51
US10223091B2Mar 5, 2019
Unaligned instruction relocation
IBM0 citations50
US9875089B2Jan 23, 2018
Unaligned instruction relocation
IBM0 citations50
US9792098B2Oct 17, 2017
Unaligned instruction relocation
IBM1 citations50
US9513832B2Dec 6, 2016
Accessing global data from accelerator devices
IBM0 citations50
CHEN TONG
7 patentsUS8146064B2Mar 27, 2012
Dynamically controlling a prefetching range of a software controlled cache
CHEN TONG21 citations92
US8997071B2Mar 31, 2015
Optimized division of work among processors in a heterogeneous processing system
CHEN TONG7 citations84
US8561044B2Oct 15, 2013
Optimized code generation targeting a high locality software cache
CHEN TONG15 citations84
US8762968B2Jun 24, 2014
Prefetching irregular data references for software controlled caches
CHEN TONG2 citations62
US8239841B2Aug 7, 2012
Prefetching irregular data references for software controlled caches
CHEN TONG5 citations62
US8214816B2Jul 3, 2012
Compiler implemented software cache in which non-aliased explicitly fetched data are excluded
CHEN TONG3 citations61
US8495307B2Jul 23, 2013
Target memory hierarchy specification in a multi-core computer processing system
CHEN TONG2 citations59