Inventor
KASHYAP CHANDRAMOULI V
US13 patents
Patents
13 patentsUS6615395B1Sep 2, 2003
Method for handling coupling effects in static timing analysis
IBM72 citations96
US7761275B2Jul 20, 2010
Synthesizing current source driver model for analysis of cell characteristics
IBM197 citations95
US7000205B2Feb 14, 2006
Method, apparatus, and program for block-based static timing analysis with uncertainty
IBM40 citations92
US6496960B1Dec 17, 2002
Driving point model utilizing a realizable reduced order circuit for determining a delay of a gate driving an interconnect with inductance
IBM30 citations92
US7346867B2Mar 18, 2008
Method for estimating propagation noise based on effective capacitance in an integrated circuit chip
IBM18 citations83
US6434729B1Aug 13, 2002
Two moment RC delay metric for performance optimization
IBM12 citations73
US6915496B2Jul 5, 2005
Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique
IBM10 citations70
US6950996B2Sep 27, 2005
Interconnect delay and slew metrics based on the lognormal distribution
IBM3 citations63
US6868533B2Mar 15, 2005
Method and system for extending delay and slew metrics to ramp inputs
IBM3 citations63
US6807659B2Oct 19, 2004
Robust delay metric for RC circuits
IBM5 citations63
US7552412B2Jun 23, 2009
Integrated circuit (IC) chip design method, program product and system
IBM2 citations62
US7475372B2Jan 6, 2009
Methods for computing Miller-factor using coupled peak noise
IBM2 citations56
US6968306B1Nov 22, 2005
Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model
IBM1 citations52