Inventor
SHENOY NARENDRA V
IN7 patents
Patents
7 patentsUS5822217AOct 13, 1998
Method and apparatus for improving circuit retiming
SYNOPSYS INC67 citations94
US6378114B1Apr 23, 2002
Method for the physical placement of an integrated circuit adaptive to netlist changes
SYNOPSYS INC28 citations89
US6397169B1May 28, 2002
Adaptive cell separation and circuit changes driven by maximum capacitance rules
SYNOPSYS INC29 citations88
US7689957B2Mar 30, 2010
Identifying and improving robust designs using statistical timing analysis
SYNOPSYS INC15 citations82
US7260807B2Aug 21, 2007
Method and apparatus for designing an integrated circuit using a mask-programmable fabric
SYNOPSYS INC11 citations80
US8042010B2Oct 18, 2011
Two-phase clock-stalling technique for error detection and error correction
SYNOPSYS INC3 citations60
US7100142B2Aug 29, 2006
Method and apparatus for creating a mask-programmable architecture from standard cells
SYNOPSYS INC0 citations48