Inventor
LEDALLA RAVICHANDER
US7 patents
⚠️ This page may combine multiple inventors who share the name “LEDALLA RAVICHANDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
6 patentsUS6763504B2Jul 13, 2004
Method for reducing RC parasitics in interconnect networks of an integrated circuit
IBM20 citations87
US9342639B1May 17, 2016
Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions
IBM12 citations79
US9607124B2Mar 28, 2017
Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints
IBM1 citations51
US7870515B2Jan 11, 2011
System and method for improved hierarchical analysis of electronic circuits
IBM1 citations50
US10169526B2Jan 1, 2019
Incremental parasitic extraction for coupled timing and power optimization
IBM0 citations49
US9858383B2Jan 2, 2018
Incremental parasitic extraction for coupled timing and power optimization
IBM1 citations49